At-speed testing of gigahertz processors using external testers may not be technically and economically feasible. Hence, there is an emerging need for low-cost high-quality self-test methodologies that can be used by processors to test themselves at-speed. Currently, built-in self-test (BIST) is the primary self-test methodology available. While memory BIST is commonly used for testing embedded memory cores, complex logic designs such as microprocessors are rarely tested with logic BIST. In this paper, we first analyze the issues associated with current hardware-based logic-BIST methodologies by applying a commercial logic-BIST tool to two processor cores. We then propose a new software-based self-testing methodology for processors, which uses a software tester embedded in the processor memory as a vehicle for applying structural tests. The software tester consists of programs for test generation and test application. Prior to the test, structural tests are prepared for processor components in the form of self-test signatures. During the process of self-test, the test generation program expands the self-test signatures into test sets and the test application program applies the tests to the components under test at the speed of the processor. Application of the novel software-based self-test method demonstrates its significant cost/fault coverage benefits and its ability to apply at-speed test while alleviating the need for high-speed testers.

Software-based self-testing methodology for processor cores

DFT advances in the Motorola's MPC7400, a PowerPC G4 microprocessor.

At-speed testing of GHz processors using external testers may not be technically and economically feasible. Hence, there is an emerging need for low-cost, high-quality self-test methodologies, which can be used by processors to test themselves at-speed. Currently, Built-In Self-Test (BIST) is the primary self-test methodology available and is widely used for testing embedded memory cores. In this paper, we report our experiences in applying a commercial BIST methodology to two processor cores and analyze the problems associated with the current hardware-based BIST methodologies. We propose a new software-based self-testing methodology for processors, which uses a software tester embedded in the processor memory as a vehicle for applying structural tests. The software tester consists of programs for test generation and test application. Prior to the test, structural tests are prepared for processor components in the form of self-test signatures. During the process of self-test, the test generation program expands the self-test signatures into test sets, and the test application program applies the tests to the components-under-test at the speed of the processor. Application of the novel software-based self-test method demonstrates its significant cost/fault coverage benefits and its ability to apply at-speed test while alleviating the need for high-speed testers.

/pdf/embedded-hardware-and-software-self-testing-methodologies-43brzmvoja.pdf

Embedded hardware and software self-testing methodologies for processor cores

Several advances have been made in the design for testability of the MPC7400, the first fourth generation PowerPC microprocessor. The memory array built-in self-test algorithms now support detecting write-recovery defects and more comprehensive diagnostics. Delay defects can be tested with scan patterns with the phased locked loop providing the at-speed launch-capture events. Several methodology and modeling improvements increased LSSD stuck-at fault test coverage. Design for manufacturability enhancements provide better tracking of initial silicon and fuse-based memory repair capabilities for improved yield and time-to-market.

DFT advances in the Motorola's MPC7400, a PowerPC/sup TM/ G4 microprocessor

We introduce a method of test generation for microprocessors at the RTL using spectral methods. Test vectors are generated for RTL faults, which are the stuck-at faults on inputs-outputs of the different modules/registers in the circuit, and the vectors are analyzed using Hadamard matrices for Walsh functions and the random noise level at each primary input. This information then helps generate vector sequences. At the gate-level, a fault simulator and an integer linear program (ILP) compact the test sequences. RTL test appraisal also helps reveal the hard-to-test parts of the circuit. An XOR observability tree was used to improve the testability of those parts. We give results for a simple accumulator-based processor named Parwan. The RTL spectral vectors produced higher coverage in shorter CPU times as compared to a gate-level ATPG

/pdf/spectral-rtl-test-generation-for-microprocessors-4j610gd29n.pdf

Spectral RTL Test Generation for Microprocessors

Digital designs, implemented in CMOS technology, have increasingly used tri-state logic (pass gates) to increase clock speed. It is also known that tri-state logic based designs have poor testability, as measured by the single stuck-at fault model, due to the proliferation of "possible-detect" faults. Design for test techniques that have been developed to address testability issues with tri-state logic designs, often incur hardware and cycle-time overheads. In this paper, we discuss the effect of one class of "possible-detect" faults and the implicit ability of a test pattern set in detecting such faults on real hardware.

C. Njinda

Papers

How seriously do you take possible-detect faults?