Logic verification tools are often used to verify a gate-level implementation of a digital system in terms of its functional specification. If the implementation is found not to be functionally equivalent to the specification, it is important to correct the implementation automatically. This paper describes a formal method for the diagnosis and correction of logic design errors in an incorrect gate-level implementation. We use Boolean equation techniques to search for potential error locations. An efficient search and pruning algorithm is developed by introducing the notion of immediate dominator set. Two correction procedures are proposed. Gate correction corrects errors such as wrong gate type, missing inverters, etc.; line correction corrects errors such as missing wires and wrong connections. Our method is robust and covers all, simple design errors described by Abadir et al. (1988). Experimental results for a set of ISCAS and MCNC benchmark circuits demonstrate the effectiveness of the proposed techniques. >

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Logic design error diagnosis and correction

An efficient variable ordering strategy for ordered binary decision diagrams (OBDD) based on interleaving the compacted clusters is proposed in this paper. The novelty of this method is to apply the divide-and-conquer approach to find a good variable ordering efficiently for circuits with a large number of I/Os. First, a given circuit is partitioned into a number of clusters according to the correlations among the fan-in cones. A good ordering for each cluster is obtained and then a good global ordering is derived by interleaving the orderings of individual clusters. In this way, the time-consuming process of searching good orderings is restricted within individual clusters each with a manageable number of input variables. This divide-and-conquer approach is able to obtain a good variable ordering more efficiently than existent methods for circuits with a large number of I/Os. One notable result from the method is that we are able to build the OBDD for the cs38417 circuit within 1000 seconds on a SPARC 20 with 128 M byte memory.

http://ieeexplore.ieee.org/iel3/2192/13662/00627903.pdf

Variable ordering for ordered binary decision diagrams by a divide-and-conquer approach

An algorithm called XOF.GA is presented which minimises Boolean mult i-output logic functions as multilevel ANDEXOR networks of two-input logic gates. It carries out symbolic simplification, and works from tlhe bottom of a binary variable decision tree to tlhe top, with variable choice determined using a genetic algorithm. Since the algorithm is multi- level in nature, it delivers more compact circuits than two-level ESOP minimisation algorithrrts, such as EXMIN2. it also finds more economical representations than the fixed polarity Ree& Muller method.

Symbolic method for simplifying AND-EXOR representations of Boolean functions using a binary-decision technique and a genetic algorithm

In GAs applied to engineering problems (in our case, the optimisation of logic circuits) the fitness function is usually complex and the fitness evaluation is time consuming. The run time is therefore a major consideration when designing a GA for optimisation, thus a look-up table for fitness evaluation is desirable. As a consequence, it is appropriate to limit the number of different chromosome fitness evaluations that any particular run of the GA will be allowed to examine. In this situation the user is uninterested in the number of generations required. It is necessary in this approach to guarantee the users that they will be able to find a good and reliable problem solution within the limited number of evaluations, and hence time available. We refer to this type of GA as a restricted evaluation GA. In this paper we suggest a number of hybrid algorithms which combine a GA with a neighbourhood search (TABU) technique to provide this performance and reliability. The effectiveness of each of these methods is compared and contrasted, and underlying principles are suggested as to why these techniques might prove to be useful in these types of problem.

Restricted Evaluation Genetic Algorithms with Tabu Search for Optimising Boolean Functions as Multi-Level AND-EXOR Networks

A soft computing tool, Genetic Algorithm, is employed here to determine the optimized system parameters of GaAs quantum wells for better high-frequency performance under hot electron condition. For a particular DC biasing field, it is possible to predict the optimum values of the system parameters, like electron temperature, channel width, carrier concentration, for realizing a particular high-frequency response characterized by a cutoff frequency, a frequency at which AC mobility falls to 0.707 of its low-frequency value. The cutoff frequency decreases with the rise of both the channel width and the carrier concentration, whereas it enhances with the increase of lattice temperature and is found to be higher at higher DC biasing fields.

Application of genetic algorithm to determine the optimized system parameters of GaAs quantum wells for better high-frequency performance under hot electron condition

An ordering-reshuffle strategy for building BDDs from a net list description is proposed. This algorithm dynamically modifies an initial ordering according to the encountered adverse situation to maintain the intermediate BDD under a reasonable size. The effectiveness of this strategy is demonstrated by building common-ordering BDDs for large circuits in the ISCAS85 benchmark including c7552 which hitherto has not been successful.

C.-S. Lin

Papers

Building BDDs with ordering-reshuffle strategy