C. Vasanthanayaki

TL;DR: The Algorithmic strength reduction technique which leads to a reduction in hardware complexity by exploiting the significances is implemented for the reduction in the power consumption and area efficient of Very Large Scale Integration (VLSI) design or iteration period in a programmable Digital Signal Processing (DSP) implementation.

TL;DR: To achieve high performance, Multiplexer Based Approximate Full Adders (MBAFA) are proposed in the inaccurate part of the HPETA design, which exhibits high speed, area efficiency, low power consumption, less Area-Delay Product (ADP) and 56.32% lesser Power-Delayed Product (PDP) than the existing conventional CSLA, SAET-CSLA, ETCSLa, HSETA, HSSSA, respectively.

TL;DR: A design of high speed energy efficient Static Segment Adder (SSA) is proposed, which improves the overall performance based on static segmentation and accuracy adjustment logic is incorporated to achieve computational accuracy for error tolerant applications.

TL;DR: A high performance Modified Static Segment approximate Multiplier (MSSM) is proposed in this paper that increases the accuracy based on the negating lower order significant information of input operands using Significance Estimator Logic Circuit (SELC).

TL;DR: A design of high speed, area, and energy efficient Static Segment On-Chip (SSOC) memory for error-tolerant applications and the proposed m-bit static segmentation algorithm is implemented and verified in Single Port Static Random Access Memory (SP SRAM) architecture.