R. Jothin

TL;DR: The Algorithmic strength reduction technique which leads to a reduction in hardware complexity by exploiting the significances is implemented for the reduction in the power consumption and area efficient of Very Large Scale Integration (VLSI) design or iteration period in a programmable Digital Signal Processing (DSP) implementation.

TL;DR: To achieve area and energy efficiency, Simplified gate level Approximate Full Adders (SAFAs) are proposed in the inaccurate part of the CEETA and CEETA1 designs and the proposed HPETM1 has a significant amount of power and area savings.

TL;DR: To achieve high performance, Multiplexer Based Approximate Full Adders (MBAFA) are proposed in the inaccurate part of the HPETA design, which exhibits high speed, area efficiency, low power consumption, less Area-Delay Product (ADP) and 56.32% lesser Power-Delayed Product (PDP) than the existing conventional CSLA, SAET-CSLA, ETCSLa, HSETA, HSSSA, respectively.

TL;DR: N-Sleep Shuffled Phase Damping (NSSPD) technique is introduced which attains an increased reliability with high energy efficiency and reduces the power consumption, energy consumption and leakage power when compared to the previous super stacking ground bounce noise reduction technique.

TL;DR: A design of high speed energy efficient Static Segment Adder (SSA) is proposed, which improves the overall performance based on static segmentation and accuracy adjustment logic is incorporated to achieve computational accuracy for error tolerant applications.