This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixed-signal ICs and emerging systems-on-a-chip (SoC) designs. But due to the increasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuous-valued external world, there is a growing need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits. This paper describes the motivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, symbolic analysis, synthesis and optimization, layout generation, yield analysis and design centering, and test. This paper summarizes the problems for which viable solutions are emerging and those which are still unsolved.

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Computer-aided design of analog and mixed-signal integrated circuits

The yield of low voltage digital circuits is found to he sensitive to local gate delay variations due to uncorrelated intra-die parameter deviations. Caused by statistical deviations of the doping concentration they lead to more pronounced delay variations for minimum transistor sizes. Their influence on path delays in digital circuits is verified using a carry select adder test circuit fabricated in 0.5 and 0.35 /spl mu/m complementary metal-oxide-semiconductor (CMOS) technologies with two different threshold voltages. The increase of the path delay variations for smaller device dimensions and reduced supply voltages as well as the dependence on the path length is shown. It is found that circuits with a large number of critical paths and with a low logic depth are most sensitive to uncorrelated gate delay variations. Scenarios for future technologies show the increased impact of uncorrelated delay variations on digital design. A reduction of the maximal clock frequency of 10% is found for, for example, highly pipelined systems realized in a 0.18-/spl mu/m CMOS technology.

The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits

In this paper, we propose a simple, yet reliable methodology to expedite yield estimation and optimization of microwave structures. In our approach, the analysis of the entire response of the structure at hand (e.g., $S$ -parameters as a function of frequency) is replaced by response surface modeling of suitably selected feature points. On the one hand, this is sufficient to determine whether a design satisfies given performance specifications. On the other, by exploiting the almost linear dependence of the feature points on the designable parameters of the structure, reliable yield estimates can be realized at low computational cost. Our methodology is verified using two examples of waveguide filters and one microstrip hairpin filter and compared with conventional Monte Carlo analysis based on repetitive electromagnetic simulations, as well as with statistical analysis exploiting linear response expansions around the nominal design. Finally, we perform yield-driven design optimizations on these filters.

Rapid Yield Estimation and Optimization of Microwave Structures Exploiting Feature-Based Statistical Analysis

Hierarchical uncertainty quantification can reduce the computational cost of stochastic circuit simulation by employing spectral methods at different levels. This paper presents an efficient framework to simulate hierarchically some challenging stochastic circuits/systems that include high-dimensional subsystems. Due to the high parameter dimensionality, it is challenging to both extract surrogate models at the low level of the design hierarchy and to handle them in the high-level simulation. In this paper, we develop an efficient analysis of variance-based stochastic circuit/microelectromechanical systems simulator to efficiently extract the surrogate models at the low level. In order to avoid the curse of dimensionality, we employ tensor-train decomposition at the high level to construct the basis functions and Gauss quadrature points. As a demonstration, we verify our algorithm on a stochastic oscillator with four MEMS capacitors and 184 random parameters. This challenging example is efficiently simulated by our simulator at the cost of only 10min in MATLAB on a regular personal computer.

Enabling High-Dimensional Hierarchical Uncertainty Quantification by ANOVA and Tensor-Train Decomposition

While process variations are becoming more significant with each new IC technology generation, they are often modeled via linear regression models so that the resulting performance variations can be captured via normal distributions. Nonlinear (e.g. quadratic) response surface models can be utilized to capture larger scale process variations; however, such models result in non-normal distributions for circuit performance which are difficult to capture since the distribution model is unknown. In this paper we propose an asymptotic probability extraction method, APEX, for estimating the unknown random distribution when using nonlinear response surface modeling. APEX first uses a binomial moment evaluation to efficiently compute the high order moments of the unknown distribution, and then applies moment matching to approximate the characteristic function of the random circuit performance by an efficient rational function. A simple statistical timing example and an analog circuit example demonstrate that APEX can provide better accuracy than Monte Carlo simulation with 10 samples and achieve orders of magnitude more efficiency. We also show the error incurred by the popular normal modeling assumption using standard IC technologies.

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Asymptotic probability extraction for non-normal distributions of circuit performance

An innovative technique which uses statistical modeling methods to simulate the mismatch of ICs components is presented in this paper. The proposed method is more general than previously published theories, being applicable up to very small device sizes. The present approach has been used to simulate the effect of mismatch on a complex analog circuit. Comparison with measured data confirms the accuracy and efficiency of the method.

http://ieeexplore.ieee.org/iel5/5467852/5467859/05468464.pdf

Statistical Modeling Techniques for thhe Simulation of Mismatch in ICs

We applied two innovative methods for statistical design optimization in the design of a CMOS OP-AMP. The most important feature of these methods is the derivation of an analytic function representing the yield surface in the design parameters space. All the required operations are implemented in an integrated CAD system and fully automatized. The results are compared with measures on several wafer lots.

http://ieeexplore.ieee.org/iel5/5468103/5468104/05468265.pdf

Yield optimization of analog ICs using 2-step analytic modeling methods

Leistungsorientiertes mehrwertiges variables Versorgungsspannungsverfahren und -system für den Entwurf von VLSI-Schaltungen

Dans cette invention, des elements de conception en bibliotheque (102) sont analyses du point de vue de la manufacturabilite en vue d'etre utilises dans la conception d'une puce a circuits integres devant etre fabriquee au moyen d'un processus de fabrication particulier. Les elements de conception en bibliotheque provenant d'une bibliotheque sont obtenus. Des attributs de manufacturabilite (104) pour les elements de conception en bibliotheque sont determines pour le processus de fabrication particulier, ces attributs de manufacturabilite contenant des attributs relatifs au rendement. Des vues en bibliotheque (106) associees aux attributs de manufacturabilite pour les elements de conception en bibliotheque sont ensuite produites, puis utilisees par un outil d'automatisation de conception electronique (EDA).

Conception de circuits integres visant a optimiser la manufacturabilite

PROBLEM TO BE SOLVED: To obtain a process for electric circuit design which temporarily analyzes an electric circuit and supplies multiple supply voltages to multiple circuit blocks of the electric circuit according to the temporary analysis SOLUTION: This method reduces the power consumption of the electric circuit 10 which has a primary supply voltage Vdd, and 1st circuit blocks 16 and 18 and a 2nd circuit block 12 This method includes a stage for determining the operation time of the 1st critical path of the 1st circuit blocks and a stage for determining the operation time of the 2nd critical path of the 2nd circuit block It is determined from those operation times that the operation time of the 1st critical path is shorter than the operation time of the 2nd critical path Then a 1st supply voltage lower than the primary supply voltage is generated as to the 1st circuit blocks in response to the decision that the operation time of the 1st critical path is shorter than the operation time of the 2nd critical path

Carlo Guardiani

Papers

Statistical Modeling Techniques for thhe Simulation of Mismatch in ICs

Yield optimization of analog ICs using 2-step analytic modeling methods

Leistungsorientiertes mehrwertiges variables Versorgungsspannungsverfahren und -system für den Entwurf von VLSI-Schaltungen

Conception de circuits integres visant a optimiser la manufacturabilite

Vlsi circuit and variable multiple supply voltage system for low-power design performance