This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixed-signal ICs and emerging systems-on-a-chip (SoC) designs. But due to the increasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuous-valued external world, there is a growing need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits. This paper describes the motivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, symbolic analysis, synthesis and optimization, layout generation, yield analysis and design centering, and test. This paper summarizes the problems for which viable solutions are emerging and those which are still unsolved.

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Computer-aided design of analog and mixed-signal integrated circuits

The yield of low voltage digital circuits is found to he sensitive to local gate delay variations due to uncorrelated intra-die parameter deviations. Caused by statistical deviations of the doping concentration they lead to more pronounced delay variations for minimum transistor sizes. Their influence on path delays in digital circuits is verified using a carry select adder test circuit fabricated in 0.5 and 0.35 /spl mu/m complementary metal-oxide-semiconductor (CMOS) technologies with two different threshold voltages. The increase of the path delay variations for smaller device dimensions and reduced supply voltages as well as the dependence on the path length is shown. It is found that circuits with a large number of critical paths and with a low logic depth are most sensitive to uncorrelated gate delay variations. Scenarios for future technologies show the increased impact of uncorrelated delay variations on digital design. A reduction of the maximal clock frequency of 10% is found for, for example, highly pipelined systems realized in a 0.18-/spl mu/m CMOS technology.

The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits

In this paper, we propose a simple, yet reliable methodology to expedite yield estimation and optimization of microwave structures. In our approach, the analysis of the entire response of the structure at hand (e.g., $S$ -parameters as a function of frequency) is replaced by response surface modeling of suitably selected feature points. On the one hand, this is sufficient to determine whether a design satisfies given performance specifications. On the other, by exploiting the almost linear dependence of the feature points on the designable parameters of the structure, reliable yield estimates can be realized at low computational cost. Our methodology is verified using two examples of waveguide filters and one microstrip hairpin filter and compared with conventional Monte Carlo analysis based on repetitive electromagnetic simulations, as well as with statistical analysis exploiting linear response expansions around the nominal design. Finally, we perform yield-driven design optimizations on these filters.

Rapid Yield Estimation and Optimization of Microwave Structures Exploiting Feature-Based Statistical Analysis

Hierarchical uncertainty quantification can reduce the computational cost of stochastic circuit simulation by employing spectral methods at different levels. This paper presents an efficient framework to simulate hierarchically some challenging stochastic circuits/systems that include high-dimensional subsystems. Due to the high parameter dimensionality, it is challenging to both extract surrogate models at the low level of the design hierarchy and to handle them in the high-level simulation. In this paper, we develop an efficient analysis of variance-based stochastic circuit/microelectromechanical systems simulator to efficiently extract the surrogate models at the low level. In order to avoid the curse of dimensionality, we employ tensor-train decomposition at the high level to construct the basis functions and Gauss quadrature points. As a demonstration, we verify our algorithm on a stochastic oscillator with four MEMS capacitors and 184 random parameters. This challenging example is efficiently simulated by our simulator at the cost of only 10min in MATLAB on a regular personal computer.

Enabling High-Dimensional Hierarchical Uncertainty Quantification by ANOVA and Tensor-Train Decomposition

While process variations are becoming more significant with each new IC technology generation, they are often modeled via linear regression models so that the resulting performance variations can be captured via normal distributions. Nonlinear (e.g. quadratic) response surface models can be utilized to capture larger scale process variations; however, such models result in non-normal distributions for circuit performance which are difficult to capture since the distribution model is unknown. In this paper we propose an asymptotic probability extraction method, APEX, for estimating the unknown random distribution when using nonlinear response surface modeling. APEX first uses a binomial moment evaluation to efficiently compute the high order moments of the unknown distribution, and then applies moment matching to approximate the characteristic function of the random circuit performance by an efficient rational function. A simple statistical timing example and an analog circuit example demonstrate that APEX can provide better accuracy than Monte Carlo simulation with 10 samples and achieve orders of magnitude more efficiency. We also show the error incurred by the popular normal modeling assumption using standard IC technologies.

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Asymptotic probability extraction for non-normal distributions of circuit performance

In this work we propose a technique for spatial and temporal partitioning of a logic circuit based on the nodes activity computed by using a simulation at an higher level of abstraction. Only those components that are activated by a given input vector are added to the detailed simulation netlist. The methodology is suitable for parallel implementation on a multi-processor environment and allows us to arbitrarily switch between fast and detailed levels of abstraction during the simulation run. The experimental results obtained on a significant set of benchmarks show that it is possible to obtain a considerable reduction in both CPU time and memory occupation together with a considerable degree of accuracy. Furthermore, the proposed technique easily fits in the existing industrial design flows.

Parallel mixed-level power simulation based on spatio-temporal circuit partitioning

A macromodel of the crosstalk effects between adjacent interconnects that takes into account the driver nonlinear behavior is presented in this paper. The macromodel is obtained by combining a reduced order representation of the equivalent impedance with coupling seen at each driver output with a network order reduction based macromodel of the overall linear interconnect network. The effectiveness of the proposed methodology is demonstrated with the analysis of the crosstalk effects on a 0.25 /spl mu/m, high density, CMOS technology.

http://ieeexplore.ieee.org/iel4/5666/15173/00694963.pdf

Nonlinear macromodels of large coupled interconnect networks

Library design elements (102) are analyzed for manufacturability to be used in designing an IC chip to be manufactured using a particular manufacturing process. The library design elements from a library are obtained. Manufacturability attributes (104) of the library design elements are determined for the particular manufacturing process, where manufacturability attributes include yield-related attributes. Library views (106) with manufacturability attributes for the library design elements are then generated, which are utilizing by an electronic design automation (EDA) tool.

IC design to optimize manufacturability

A method for simulating an integrated circuit includes dividing the integrated circuit into a plurality of independent subcircuits using a digital simulator, electrically simulating each of the independent subcircuits for a simulation result, and linking together the simulation results. By splitting the simulation of the integrated circuit into a plurality of simulations of smaller independent subcircuits, the electrical simulation is faster and can be performed in parallel since each subcircuit is independent.

Method for the electric dynamic simulation of VLSI circuits

We analyze the integration of an RT-level power estimation tool, RTPOW into an industrial design flow. We address important practical issues such as the extraction of structural and functional information and the use of simulation data to derive probabilistic information. We present the results obtained with RTPOW on a realistic design that demonstrates the effectiveness of our tool.

Carlo Guardiani

Papers

Parallel mixed-level power simulation based on spatio-temporal circuit partitioning

Nonlinear macromodels of large coupled interconnect networks

IC design to optimize manufacturability

Method for the electric dynamic simulation of VLSI circuits

RTL power estimation in an industrial design flow