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Carlos Valderrama

Researcher at University of Mons

Publications -  90
Citations -  1026

Carlos Valderrama is an academic researcher from University of Mons. The author has contributed to research in topics: Field-programmable gate array & Hardware architecture. The author has an hindex of 18, co-authored 88 publications receiving 929 citations. Previous affiliations of Carlos Valderrama include Federal University of Pernambuco & Faculté polytechnique de Mons.

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A Multi-Resolution FPGA-Based Architecture for Real-Time Edge and Corner Detection

TL;DR: A performance analysis of the FPGA and the GPU implementations, and an extra CPU reference implementation, shows the competitive throughput of the proposed architecture even at a much lower clock frequency than those of the GPU and the CPU.
Proceedings ArticleDOI

A unified model for co-simulation and co-synthesis of mixed hardware/software systems

TL;DR: This approach addresses the modeling of communication between the hardware and software modules at different abstraction levels and for different design tools by using a multi-view library concept in order to hide specific hardware/software implementation details and communication schemes.
Journal ArticleDOI

Objective Study of Sensor Relevance for Automatic Cough Detection

TL;DR: In this paper, the authors evaluated the performance of ECG, thermistor, chest belt, accelerometer, contact, and audio microphones for the detection of chronic chronic cough disease using three stages: mutual information conveyed by the features, ability to discriminate at the frame level cough from these latter other sources of ambiguity, and ability to detect cough events.
Posted Content

Objective Study of Sensor Relevance for Automatic Cough Detection

TL;DR: The proposed approach is shown to clearly outperform the commercial Karmelsonix system which achieved a specificity of 95.3% and a sensitivity of 64.9% in this latter experiment.
Journal ArticleDOI

A Survey and Taxonomy of FPGA-based Deep Learning Accelerators

TL;DR: This paper briefly review recent work related to the implementation of deep learning algorithms in FPGAs, and analyzes and compares the design requirements and features of existing topologies to finally propose development strategies and implementation architectures for better use of FPGA-based deep learning topologies.