Shuffled versions of iterative decoding of low-density parity-check codes and turbo codes are presented. The proposed schemes have about the same computational complexity as the standard versions, and converge faster. Simulations show that the new schedules offer better performance/complexity tradeoffs, especially when the maximum number of iterations has to remain small.

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Shuffled iterative decoding

A process for generating a number representative of an analogue data source (ADS) in which during enrolment a distinctive characteristic of the ADS is measured to obtain physical data (PD). Part of the PD is used to generate a physical value (PV) representative of the ADS. An error correction algorithm (ECA) is applied to the PV to generate error correction data (ECD), which is transformed, using another part of the PD, to generate transform data. During subsequent regeneration of the PV, the distinctive characteristic is re-measured to generate a new set of PD, and a PV is generated using the same part of the PD physical data as was used during enrolment. ECD is generated by transforming the transform data, using the same part of the PD as was used to transform the ECD during enrolment. The ECA uses the regenerated ECD to correct errors in the PV representative of the ADS.

Data processing apparatus and method

An apparatus, system, and method are disclosed for solid-state storage as cache for high-capacity, non-volatile storage. The apparatus, system, and method are provided with a plurality of modules including a cache front-end module and a cache back-end module. The cache front-end module manages data transfers associated with a storage request. The data transfers between a requesting device and solid-state storage function as cache for one or more HCNV storage devices, and the data transfers may include one or more of data, metadata, and metadata indexes. The solid-state storage may include an array of non-volatile, solid-state data storage elements. The cache back-end module manages data transfers between the solid-state storage and the one or more HCNV storage devices.

Apparatus, system, and method for solid-state storage as cache for high-capacity, non-volatile storage

An apparatus, system, and method are disclosed for managing eviction of data. A cache write module stores data on a non-volatile storage device sequentially using a log-based storage structure having a head region and a tail region. A direct cache module caches data on the non-volatile storage device using the log-based storage structure. The data is associated with storage operations between a host and a backing store storage device. An eviction module evicts data of at least one region in succession from the log-based storage structure starting with the tail region and progressing toward the head region.

Apparatus, system, and method for managing eviction of data

A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message.

Low density parity check decoder for regular LDPC codes

A data communication system has a combiner circuit that combines a set of information symbols with error correction codes and that generates a set of product codes that are at least three dimensional. A communication channel receives the set of product codes and provides the set of product codes with errors after a channel delay. A channel detector receives the set of product codes with the errors and generates a channel detector output. An error correction circuit receives the channel detector output and iteratively removes the errors to provide a set of reproduced information symbols with a reduced number of the errors.

Data communication system with multi-dimensional error-correction product codes

In this letter, we propose an efficient decoding algorithm for turbo product codes as introduced by Pyndiah. The proposed decoder has no performance degradation and reduces the complexity of the original decoder by an order of magnitude. We concentrate on extended Bose-Chaudhuri-Hocquengem codes as the constituent row and column codes because of their already low implementation complexity. For these component codes, we observe that the weight and reliability factors can be fixed, and that there is no need for normalization. Furthermore, as opposed to previous efficient decoders, the newly proposed decoder naturally scales with a test-pattern parameter p that can change as a function of iteration number, i.e., the efficient Chase algorithm presented here uses conventionally ordered test patterns, and the syndromes, even parities, and extrinsic metrics are obtained with a minimum number of operations.

An efficient Chase decoder for turbo product codes

A system is described for decoding product codes. The system includes logic configured to pass reliability determinations made while decoding symbols using first parity information, to use in decoding the symbols using second parity information, while substantially simultaneously passing the reliability determinations made while decoding the symbols using the second parity information, to use in decoding the symbols using the first parity information.

Parallel decoder for product codes

There has been intensive focus on turbo product codes (TPCs) which have low decoding complexity and achieve near-optimum performances at low signal-to-noise ratios. Different than the original TPC decoder, which performs row and column decoding in a serial fashion, we propose a parallel decoder structure. Simulation results show that with this approach, decoding latency of TPCs can be halved while maintaining virtually the same performance level.

A parallel decoder for low latency decoding of turbo product codes

Multimode fiber links suffer from intermodal dispersion, which, at high data rates, produces intersymbol interference in the received optical signal. Without signal processing or equalization, this limits the achievable data rates. We consider the combination of a spatially resolved equalizer (SRE) (in the optical domain) and forward error correction (FEC) to increase the achievable data rates and reliability on these links. Our performance results obtained with actual measured impulse responses show that SRE and FEC on a multimode fiber link enable a significant increase (about 2.5 times) in data rate and/or a reduction in bit error rate (BER) at relatively low cost. Furthermore, we show that improvements in data rate and reliability are generally not possible using FEC alone, making the SRE/FEC combination a cost-effective, attractive approach.

Cenk Argon

Papers

Data communication system with multi-dimensional error-correction product codes

An efficient Chase decoder for turbo product codes

Parallel decoder for product codes

A parallel decoder for low latency decoding of turbo product codes

Spatially resolved equalization and forward error correction for multimode fiber links