Patent
Parallel decoder for product codes
Cenk Argon,Steven W. McLaughlin +1 more
TLDR
In this article, a system for decoding product codes is described, which includes logic configured to pass reliability determinations made while decoding symbols using first parity information, to use in decoding the symbols using second parity information.Abstract:
A system is described for decoding product codes. The system includes logic configured to pass reliability determinations made while decoding symbols using first parity information, to use in decoding the symbols using second parity information, while substantially simultaneously passing the reliability determinations made while decoding the symbols using the second parity information, to use in decoding the symbols using the first parity information.read more
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Apparatus, system, and method for solid-state storage as cache for high-capacity, non-volatile storage
TL;DR: In this article, an apparatus, system, and method for solid-state storage as cache for high-capacity, non-volatile storage is described. But the system is based on a cache front-end and a cache back-end.
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Apparatus, system, and method for caching data on a solid-state storage device
David Flynn,John Strasser,Jonathan Thatcher,David Atkisson,Michael Zappe,Joshua Aune,Kevin Vigor +6 more
TL;DR: In this paper, an apparatus, system, and method are disclosed for an caching data using a solid-state storage device, where metadata indicates what data in the cache is valid, as well as information about what data from the nonvolatile cache has been stored in the backing store.
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Apparatus, system, and method for destaging cached data
David Atkisson,David Flynn +1 more
TL;DR: In this paper, an apparatus, system, and method are disclosed for destaging cached data in a nonvolatile solid-state storage device (NVS) with a cache controller.
References
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Patent
Method for detecting information bits processed by concatenated block codes
TL;DR: In this paper, the transmitted bits are coded according to the product of at least two systematic block codes, and an iterative decoding is applied in order to determine, at each code word search step, a data matrix and a decision matrix which are used for the following step.
Patent
Process for transmitting information bits with error correction coding, coder and decoder for the implementation of this process
Ramesh Pyndiah,P. Adde +1 more
TL;DR: In this article, the bits transmitted are coded according to the product of at least two systematic block codes, and the coding and decoding circuits are rendered programmable by a shortening technique allowing selection of the number k-X of non-redundant information bits per block to be coded.
Patent
Frame control encoder/decoder for robust OFDM frame transmissions
TL;DR: In this article, an encoder/decoder scheme for robust transmission of PHY layer frame control information in OFDM frames is proposed, where a product encoder (100) is used to form a product code block/matrix that is based on a hamming code codeword set having properties of symmetry.
Patent
Turbo product code decoder
TL;DR: In this article, a turbo product code decoder for decoding multi-dimensional coding schemes is presented. But the decoder is configured for receiving soft decision values, and the soft difference values from each axis-iteration are then summed with the original soft decision value in decoding each of the other axis.