Showing papers by "Chandra Mouli published in 2017"

Integrated Structures Comprising Vertical Channel Material and Having Conductively-Doped Semiconductor Material Directly Against Lower Sidewalls of the Channel Material, and Methods of Forming Integrated Structures

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels Upper conductive levels are memory cell levels, and a lower conductive level is a select device level Conductively-doped semiconductor material is under the select device level Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion Some embodiments include methods of forming integrated structures

Low capacitance through substrate via structures

Abstract: Apparatuses and methods are disclosed herein for the formation of low capacitance through substrate via structures. An example apparatus includes an opening formed in a substrate, wherein the opening has at least one sidewall, a first dielectric at least formed on the sidewall of the opening, a first conductor at least formed on the first dielectric, a second dielectric at least formed on the first conductor, and a second conductor at least formed on a sidewall of the second dielectric.

Apparatuses with compensator lines laid out along wordlines and spaced apart from wordlines by dielectric, compensator lines being independently controlled relative to the wordlines providing increased on-current in wordlines, reduced leakage in coupled transistors and longer retention time in coupled memory cells

Abstract: Some embodiments include an apparatus which has a wordline coupled with a transistor gate, and which has a compensator line extending along the wordline and spaced from the wordline by a dielectric region A driver is coupled with the wordline, and a controller is coupled with the compensator line The wordline is coupled with access transistors, and is operated at a first voltage while the access transistors are in an OFF state The compensator line is operated at a second voltage while the wordline is at the first voltage; with the second voltage being greater than the first voltage The wordline is operated at a third voltage while the access transistors are in an ON state, and the compensator line is operated at a fourth voltage while the wordline is at the third voltage The third voltage may or may not be greater than the fourth voltage