This brief develops a novel hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) gate driver with short rising and falling times. The driving capability of the a-Si:H device is improved owing to the enlarged gate voltages by the two-step-bootstrapping structure of the proposed gate driver. The measured rising time, falling time, and voltage swing of the output waveform are $2.05~\mu$ s, 1.31 $\mu$ s, and 27.1 V, respectively, after an accelerated lifetime test at 70 °C for 120 h.

Gate Driver Based on a-Si:H Thin-Film Transistors With Two-Step-Bootstrapping Structure for High-Resolution and High-Frame-Rate Displays

A hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) gate driver on array with low-level holding TFTs (LLH TFTs) biased under bipolar pulse is investigated. It is shown that the bipolar bias at low frequency significantly alleviates the threshold voltage shift of the LLH TFTs. As a result, the lifetime of the proposed gate driver is demonstrated to be several times of that under the conventional unipolar pulse bias. In addition, the improvement in the lifetime becomes more significant at the higher work temperature. The liquid crystal display television panels (32-in, $1366\times \textrm {RGB}\times 768$ ) with the proposed a-Si:H gate drivers integrated on array are manufactured, and the feasibility of the proposed driving scheme is well verified.

Integrated a-Si:H Gate Driver With Low-Level Holding TFTs Biased Under Bipolar Pulses

This paper proposes a new hydrogenated amorphous silicon thin-film-transistor-based (a-Si:H TFT-based) gate driver circuit that uses the time-division driving method to ameliorate the display-to-touch crosstalk. The proposed work utilizes a recharging circuit to discharge the voltage on the gate node of the driving TFT when the touch sensing starts with the purpose of suppressing the long-term stress of the driving TFT, and charges the gate node of the driving TFT again before the end of the touch-sensing period to enhance the driving capability of the gate driver circuit. Furthermore, the proposed gate driver circuit achieves bidirectional transmission and an adjustable reporting rate of touch sensing. Measurements verify that the threshold voltage shift of the driving TFT is suppressed from 4.8 to 2.9 V after 120 h of stress at 85 °C and the output waveforms of the proposed gate driver circuits are generated correctly with forward transmission, backward transmission, and pausing in different stages. Moreover, the measured output waveforms are stable without distortion after 360 h reliability test at 85 °C. Consequently, the proposed gate driver circuit is suitable for use in 5.46-in full high-definition panels with in-cell touch technology.

Bidirectional Gate Driver Circuit Using Recharging and Time-Division Driving Scheme for In-Cell Touch LCDs

Amorphous IGZO thin-film transistors (TFTs) in an etch stop layer (ESL) structure was processed on 2500 mm $\times $ 2200 mm size substrate. The fabricated devices exhibit enhancement mode characteristics, and excellent uniformity over large area. The presented good operational stabilities under both positive gate bias temperature stress (PBTS) and negative gate bias temperature stress (NBTS) tests can well meet the requirements for pixel switching. However, considering even threshold voltage shift under long term positive bias stress might affect proper operation of the gate driver on array (GOA), a design with a pulse gating scheme is proposed, consisting of 13 TFTs and 1 capacitor, to avoid long term continuous bias stressing of the TFT. With the proposed GOA design, a 32-inch QUHD ( $7680\times 4320$ ) high-resolution liquid crystal display (LCD) panel with a 7 mm wide bezel is achieved. The reliability of the GOA circuit is well proved through standard aging tests.

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Robust Gate Driver on Array Based on Amorphous IGZO Thin-Film Transistor for Large Size High-Resolution Liquid Crystal Displays

A new back-channel-etched process for the fabrication of amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) is demonstrated, in which a conductive Nb doped TiO
 2
 (TNO) thin film is used to serve as protective layer for the a-IGZO active layer. It is shown that the TNO film provides the active layer with excellent protection even when the thickness is only 1 nm. With treatment by N
 2
O plasma +200°C annealing, the conductive TNO can be converted into an insulator to serve as an in situ passivation layer. Besides, by the introduction of the TNO layer, the source-drain parasitic resistance of the BCE process fabricated TFTs is significantly reduced and the positive bias stress stability is improved as well.

Nb Doped TiO2 Protected Back-channel-etched Amorphous Ingazno Thin Film Transistors

Threshold voltage shift ( $\Delta V_{\mathrm{ TH}}$ ) effect of hydrogenated amorphous silicon thin-film transistors under bipolar pulse bias stress (BPBS) is investigated. The dependence of the $\Delta V_{\mathrm{ TH}}$ effect on the signal pulsewidth, stress temperature, and negative pulse voltage magnitude of the BPBS is systematically measured, and explained by the charge trapping and detrapping theory. Results show that the BPBS leads to a noticeably suppressed $\Delta V_{\mathrm{ TH}}$ , compared with the conventional unipolar pulse bias stress. It is suggested that the BPBS with proper negative pulse voltage magnitude and low pulse frequency is an effective way of suppressing $\Delta V_{\mathrm{ TH}}$ , especially when the thin-film transistors work relatively at high temperature.

Threshold Voltage Shift Effect of a-Si:H TFTs Under Bipolar Pulse Bias

A high reliable amorphous silicon gate driver with shared dual pull-down units is proposed and fabricated for large-sized TFT-LCD applications. A special unit in the driver is designed to generate bipolar pulse bias for low-level holding TFTs to suppress the threshold voltage shift, which achieves 40.5% and 34.8% improvement compared with conventional DC and unipolar pulse bias respectively according to measurement results.

P‐12: A‐Si:H TFT Gate Driver with Shared Dual Pull‐Down Units for Large‐Sized TFT‐LCD Applications

The present invention provides a gate driver on array (GOA) circuit and a display panel with the GOA circuit. The driver circuit includes multiple stages of gate driver units and multiple stages of supplementary gate driver units connected in cascade, in which the nth stage gate driver unit includes a driving unit ( 42 ) and a pull-down unit ( 44 ) and the mth stage supplementary gate driver unit includes a supplementary driving unit ( 52 ) and a supplementary pull-down unit ( 54 ). The GOA circuit according to the present invention adopts a dual-pull-down architecture so that thin-film transistors contained in pull-down units and supplementary pull-down units of the circuit can be set in an operation environment featuring dual polarity electrical biasing to effectively suppress threshold voltage drifting of the thin-film transistors of the pull-down units and the supplementary pull-down units and extend the lifespan of circuit thereby making the circuit better meet the needs of large- and medium-sized display panels. Further, the circuit has a simple structure and reduced power consumption and is also fit to low temperature and high temperature operations.

Gate driver on array (GOA) circuit and display panel with same

An integrated gate drive circuit and a display panel comprising the integrated gate drive circuit. The drive circuit comprises multiple levels of gate drive units that are cascaded and multiple levels of additional gate drive units, wherein the gate drive unit of level n comprises a drive unit (42) and a pull-down unit (44), and the additional gate drive unit of level m comprises an additional drive unit (52) and an additional pull-down unit (54). The integrated gate drive circuit uses a dual-pull-down structure, enables a thin film transistor in the pull-down unit and the additional pull-down unit in the circuit to be located in a working environment with a bipolar voltage offset, effectively suppresses a threshold voltage drift of the thin film transistor in the pull-down unit and the additional pull-down unit, prolongs service lift of the circuit, and enables the circuit to better meet requirements of large- and medium-sized display panels. In addition, the circuit has a simple structure and low power consumption, and applies low-temperature and high-temperature running.

Chang-Yeh Lee

Papers

Integrated a-Si:H Gate Driver With Low-Level Holding TFTs Biased Under Bipolar Pulses

Threshold Voltage Shift Effect of a-Si:H TFTs Under Bipolar Pulse Bias

P‐12: A‐Si:H TFT Gate Driver with Shared Dual Pull‐Down Units for Large‐Sized TFT‐LCD Applications

Gate driver on array (GOA) circuit and display panel with same

Integrated gate drive circuit and display panel comprising integrated gate drive circuit