Machine Learning is the study of methods for programming computers to learn. Computers are applied to a wide range of tasks, and for most of these it is relatively easy for programmers to design and implement the necessary software. However, there are many tasks for which this is difficult or impossible. These can be divided into four general categories. First, there are problems for which there exist no human experts. For example, in modern automated manufacturing facilities, there is a need to predict machine failures before they occur by analyzing sensor readings. Because the machines are new, there are no human experts who can be interviewed by a programmer to provide the knowledge necessary to build a computer system. A machine learning system can study recorded data and subsequent machine failures and learn prediction rules. Second, there are problems where human experts exist, but where they are unable to explain their expertise. This is the case in many perceptual tasks, such as speech recognition, hand-writing recognition, and natural language understanding. Virtually all humans exhibit expert-level abilities on these tasks, but none of them can describe the detailed steps that they follow as they perform them. Fortunately, humans can provide machines with examples of the inputs and correct outputs for these tasks, so machine learning algorithms can learn to map the inputs to the outputs. Third, there are problems where phenomena are changing rapidly. In finance, for example, people would like to predict the future behavior of the stock market, of consumer purchases, or of exchange rates. These behaviors change frequently, so that even if a programmer could construct a good predictive computer program, it would need to be rewritten frequently. A learning program can relieve the programmer of this burden by constantly modifying and tuning a set of learned prediction rules. Fourth, there are applications that need to be customized for each computer user separately. Consider, for example, a program to filter unwanted electronic mail messages. Different users will need different filters. It is unreasonable to expect each user to program his or her own rules, and it is infeasible to provide every user with a software engineer to keep the rules up-to-date. A machine learning system can learn which mail messages the user rejects and maintain the filtering rules automatically. Machine learning addresses many of the same research questions as the fields of statistics, data mining, and psychology, but with differences of emphasis. Statistics focuses on understanding the phenomena that have generated the data, often with the goal of testing different hypotheses about those phenomena. Data mining seeks to find patterns in the data that are understandable by people. Psychological studies of human learning aspire to understand the mechanisms underlying the various learning behaviors exhibited by people (concept learning, skill acquisition, strategy change, etc.).

Machine learning

Clock power, skew and maximum latency are three key metrics for clock distribution in low-power and high-performance designs. An H-tree offers minimum clock skew and good robustness against variations, but at the cost of large wirelength and clock power. On the other hand, a “fishbone” clock network with spine-ribs structures has smaller wirelength, latency and clock power, but larger skew, as compared to an H-tree. No previous work enables systematic exploration of the regime between H-tree and spine to achieve an optimal tradeoff among clock power, skew, and latency. In this paper, we study the concept of a generalized H-tree (GH-tree)—a topologically balanced tree with an arbitrary sequence of branching factors—and propose a dynamic programming-based method to determine optimal clock power, skew, and latency, in the space of GH-tree solutions. Our method co-optimizes clock tree topology and buffering along branches according to fitted electrical models. We further propose a balanced ${K}$ -means clustering and a linear programming (LP)-guided buffer placement approach to embed the GH-tree with respect to a given sink placement. We validate our solutions in commercial clock tree synthesis (CTS) tool flows, in a commercial foundry’s 28LP technology. The results show up to 30% clock power reduction while achieving similar skew and maximum latency as CTS solutions from recent versions of leading commercial place-and-route tools. Our proposed approach also achieves up to 56% clock power reduction while achieving similar skew and maximum latency as compared to CTS solutions from a state-of-the-art academic tool.

https://par.nsf.gov/servlets/purl/10171002

Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution

A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing.

Eda tool and method for conflict detection during multi-patterning lithography

Clock network power reduction is critical in modern SoC designs. Application of flop trays (i.e., multi-bit flip-flops) can significantly reduce the number of sinks in a clock network, and thus reduce the number of clock buffers, clock wirelength, and clock network power. Shared inverters within flop trays also reduce power at the flip-flop level. However, large-size flop trays typically induce placement and routing congestion, and impose additional placement constraints on their fanin/fanout logic cones; this results in power overheads on datapaths. At the same time, to our knowledge, few previous works have studied flop trays with more than four bits. The "chicken-and-egg" loop between flop tray generation and placement optimization is another challenge to flop tray-based design [7]. In this work, we propose an optimization flow to generate and place flop trays from a library of arbitrary given sizes and aspect ratios (ARs), to achieve clock network power reduction. Our optimization starts with an initial placement solution using only single-bit flops. It then performs capacitated K-means clustering to generate solutions with different flop tray sizes and ARs. More specifically, we iteratively use (i) min-cost flow to cluster flops, and (ii) a linear programming-based optimization to determine locations of the generated flop trays. Last, we formulate an integer linear program to select the best combination of flop tray solutions (i.e., sizes and placements) with minimum displacement and number of isolated sinks. Our optimization is aware of flop tray sizes and ARs, as well as timing-critical start-end pairs. Results in foundry 28FDSOI technology show up to 32% total block power reduction as compared to designs using only single-bit flops, up to 16% total block power reduction over designs with flop trays generated by logical clustering during synthesis, and 13% clock power reduction on average compared to the previous work in [10].

Improved flop tray-based design implementation for power reduction

A slew-driven clock tree synthesis (SLECTS) methodology is proposed for nanoscale technologies where the interconnect resistance dominates device resistance, thereby increasing the challenge of satisfying the slew constraint. This issue is exacerbated at lower voltages due to degraded drive ability of the clock buffers. A paradigm shift from the traditional delay (and skew)-driven approaches to the proposed slew-driven methodology is therefore required. SLECTS is developed in this paper to satisfy tight slew constraints, which can be costly or infeasible with delay (skew)-driven methodologies and reduce the power dissipation of the clock tree, since the slew and skew constraints are simultaneously and methodically considered. Experimental results performed on an industrial circuit with more than 1M gates designed in 28-nm technology demonstrate that clock power is reduced by approximately 15% as compared to a commercial clock tree synthesis tool under similar slew and skew constraints.

SLECTS: Slew-Driven Clock Tree Synthesis

As VLSI technology continuously scales down, buffered clock tree synthesis (CTS) has become increasingly critical in an attempt to generate a high-performance synchronous chip design. This paper presents a novel obstacle-avoiding CTS approach with slew constraints satisfied and signal polarity corrected. We build a look-up table through NGSPICE simulation to achieve accurate buffer delay and slew, which guarantees that the final skew after NGSPICE simulation is as satisfactory as expected. Aiming at skew optimization under constraints of slew and obstacles, our CTS approach features the clock tree construction stage with the obstacle-aware topology generation algorithm called OBB, balanced insertion of candidate buffer positions and a fast heuristic buffer insertion algorithm. With an overall view on obstacles to explore the global optimization space, our CTS approach effectively overcomes the negative influence on skew brought by the obstacles. Experimental results show the effectiveness of our CTS approach with significantly improved skew and latency by 69.0% and 72.0% on average. In addition, the accuracy of the look-up table is demonstrated through the huge skew reduction by 87.3% on average. Moreover, our OBB heuristic algorithm obtains 53.2% improvement in skew than the classic balanced bipartition algorithm.

Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion

Clock networks dissipate a significant fraction of the entire chip power budget. Therefore, the optimization for power consumption of clock networks has become one of the most important objectives in high performance IC designs. In contrast to most of the traditional studies that handle this problem with clock routing or buffer insertion strategy, this paper proposes a novel register clustering methodology in generating the leaf level topology of the clock tree to reduce the power consumption. Three register clustering algorithms called KMR, KSR and GSR are developed and a comprehensive study of them is discussed in this paper. Meanwhile, a buffer allocation algorithm is proposed to satisfy the slew constraint within the clusters at a minimum cost of power consumption. We integrate our algorithms into a classical clock tree synthesis (CTS) flow to test the register clustering methodology on ISPD 2010 benchmark circuits. Experimental results show that all the three register clustering algorithms achieve more than 20% reduction in power consumption without affecting the skew and the maximum latency of the clock tree. As the most effective method among the three algorithms, GSR algorithm achieves a 31% reduction in power consumption as well as a 4% reduction in skew and a 5% reduction in maximum latency. Moreover, the total runtime of the CTS flow with our register clustering algorithms is significantly reduced by almost an order of magnitude.

Register Clustering Methodology for Low Power Clock Tree Synthesis

Clock networks dissipate a significant fraction of the entire chip power budget. In contrast to most of the traditional works that handle the power optimization problem with clock routing or buffer sizing, we propose a novel register clustering methodology for power reduction of clock trees. Moreover, a fast three-stage clock tree synthesis (CTS) approach based on register clustering is presented to verify the validity of the methodology. By comparison with the state-of-the-art low power CTS research works Contango2.0 [21] and the CTS of Purdue University [16], our three-stage CTS approach achieves 1.30×, 1.07× smaller power consumption while exhibiting 2.01×, 1.52× smaller skew. Furthermore, the runtime of our CTS approach is 17.36×, 8.16× shorter than that of [21] and [16] respectively.

Fast synthesis of low power clock trees based on register clustering

The invention discloses a layout bipartition method, aiming at solving the defect that the product quality is lowered due to overlarge layout density in the conventional photoetching technology. The layout bipartition method disclosed by the invention comprises the following steps of: partitioning graphs of which the graph pitch is less than a minimal photoetching pitch, into two sub layouts, and obtaining a layout graph through two photoetching operations; when the graph pitch in the sub layout is still less than the minimal photoetching pitch after two sub layouts are formed, partitioning the graphs in the layouts into at least two sub graphs, partitioning each sub graph of which the pitch is less than the minimal photoetching pitch, into two sub layouts by using the sub graph as a unit, and obtaining the layout graph after carrying out two photoetching operations on a substrate; and labeling the layout region where sub layouts cannot be obtained by using a partitioning method. The layout bipartition method disclosed by the invention is applied to the fields of layout design and product manufacture of large-scale integration circuits, and has the characteristics of convenience for use and high accuracy.

Layout bipartition method

Clock networks dissipate a significant fraction of the entire chip power budget. Therefore, the optimization for power consumption of clock networks has become one of the most important objectives in high performance IC designs. In contrast to most of the traditional works that handle this problem with clock routing or buffer sizing, this paper proposes a novel register clustering algorithm in generating the leaf level topology of the clock tree to reduce the power consumption. Aiming to guarantee the stability of our register clustering algorithm, an effective initialization algorithm called “K-Splitting” and a “Pseudo Center” technology are developed. Meanwhile, a buffer allocation algorithm is proposed to satisfy the slew constraints within the clusters at a minimum cost of power consumption. We implement the clock tree synthesis (CTS) flow in [2] to test our approach on ISPD'10 benchmark circuits. Experimental results show that our register clustering algorithm achieves a 29.0% reduction in power consumption as well as a 5.7% reduction in max latency without affecting the clock skew. Moreover, the total runtime of the CTS flow with our register clustering algorithm is significantly reduced by 87.3%.

Chao Deng

Papers

Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion

Register Clustering Methodology for Low Power Clock Tree Synthesis

Fast synthesis of low power clock trees based on register clustering

Layout bipartition method

A register clustering algorithm for low power clock tree synthesis