The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications.

Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements

A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed p+ region to form a p-n diode in the substrate underlying the gate of the transistor. Further, the wordline is formed from a buried diffusion N+ layer while the column bitline is formed from a counterdoped polysilicon layer.

High density semiconductor memory cell and memory array using a single transistor and having counter-doped poly and buried diffusion wordline

A configurable computing architecture (10) has its functionality controlled by a combination of static and dynamic control, wherein the configuration is referred to as static control and instructions are referred to as dynamic control. A reconfigurable data path (12) has a plurality of elements including functional units (32, 36), registers (30), and memories (34) whose interconnection and functionality is determined by a combination of static and dynamic control. These elements are connected together, using the static configuration, into a pipelined data path that performs a computation of interest. The dynamic control signals (21) are suitably used to change the operation of a functional unit and the routing of signals between functional units. The static control signals (23) are provided each by a static memory cell (62) that is written by a host (13). The controller (14) generates control instructions (16) that are interpreted by a control path (18) that computes the dynamic control signals. The control path is configured statically for a given application to perform the appropriate interpretation of the instructions generated by the controller. By using a combination of static and dynamic control information, the amount of dynamic control used to achieve flexible operation is significantly reduced.

Reconfigurable computing architecture for providing pipelined data paths

A reconfigurable integrated circuit is provided wherein the available hardware resources can be optimised for a particular application. Dynamically reconfiguring (in both real-time and non real-time) the available resources and sharing a plurality of processing elements with a plurality of controller elements achieve this. In a preferred embodiment the integrated circuit includes a plurality of processing blocks, which interface to a reconfigurable interconnection means. A processing block has two forms, namely a shared resource block and a dedicated resource block. Each processing block consists of one or a plurality of controller elements and a plurality of processing elements. The controller element and processing element generally comprise diverse rigid coarse and fine grained circuits and are interconnected through dedicated and reconfigurable interconnect. The processing blocks can be configured as a hierarchy of blocks and or fractal architecture.

Reconfigurable integrated circuit

A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal processing region may include a multiplier stage and one ore more stages that can operate in combination with the multiplier stage. The digital signal processing region has a plurality of modes such as for providing multiply-and-accumulate operation, multiply-and-add operation, etc.

Devices and methods with programmable logic and digital signal processing regions

An architecture for information processing devices which allows the construction of low cost, high performance systems for specialized computing applications involving sensor data processing. The reconfigurable processor architecture of the invention uses a programmable logic structure called an Adaptive Logic Processor (ALP). This structure is similar to an extendible field programmable gate array (FPGA) and is optimized for the implementation of program specific pipeline functions, where the function may be changed any number of times during the progress of a computation. A Reconfigurable Pipeline Instruction Control (RPIC) unit is used for loading the pipeline functions into the ALP during the configuration process and coordinating the operations of the ALP with other information processing structures, such as memory, I/O devices, and arithmetic processing units. Multiple components having the reconfigurable architecture of the present invention may be combined to produce high performance parallel processing systems based on the Single Instruction Multiple Data (SIMD) architecture concept.

Reconfigurable computer architecture for use in signal processing applications

A bus transceiver system transfers data among a plurality (N) of system components. The system includes N toggle bus transceiver circuits (TBTi, for i=0 through N-1), each of which corresponds to a respective one of the system components. Each toggle bus transceiver circuit has bi-directional driver circuitry which has M first terminals (Di,j, for j=0 through M-1). Each of the M first terminals are coupled to a respective bit of the system component to which that toggle bus transceiver circuit corresponds. Each toggle bus tranceiver circuit further has M second terminals (Pi,j). Driver switch circuitry of each toggle bus transceiver circuit selectively connects each of the M first terminals to at least one of said M second terminals. In a first mode, the driver circuitry drives in a first direction and in a second mode, the driver circuitry drives in a second direction. Repeater of each toggle bus transceiver circuit has M third terminals (Qi,j) and M latch circuits (Li,j). Repeater switch circuitry selectively connects each of the M third terminals to at least one of the latch circuits. In the first mode, each latch circuit latches a data signal provided at the third terminal to which the latch circuit is connected, and in the second mode, the latch circuit provides a data signal latched by the latch circuit to the third terminal to which said latch circuit is connected. A permuted interconnect network couples the second terminals of the toggle bus transceiver circuit bi-directional driver circuitry to the third terminals of the toggle bus transceiver circuit repeater circuitry for permuted signal transfer therebetween.

Toggle bus circuit

The component includes an adaptive logic processor. This includes a number of individual configurable logic cells (150) in an arrangement containing several vertical columns of configurable cells and several horizontal rows of configurable cells. A set of control lines (134) is provided to carry control signals. A set of data lines (132) is provided to transmit data between a pipeline segment (160) and a logic cell reconfiguration control. The pipeline segment (160) contains a quantity of logic cells and is positioned along the vertical length of the arrangement. The sets of control lines (134) and data lines (132) extend over several columns of the arrangement allowing the pipe line segment (160) to be disposed in several horizontal positions in the arrangement. The logic cell reconfiguration control controls the configuration of the cells (150) to form the pipeline segment (160) and to carry out the logic functions through the configured cells by transmitting commands and data over the control and data lines.

Reconfigurable computer component with adaptive logic processor

In a 4x4 system, there are four bits per word and four TBT components (TBT4,0 to TBT4,3). The components are connected together through a permutation network (P.0 to P.15), and the bus transmitter-receiver (TBT) is inserted into each TBT component. When all the TBT components have the same configuration, the system is designated as a homogeneous network, otherwise it is a heterogeneous network which has a subset of bus capabilities to improve the characteristics of the system, while the transmission of more than one word is made possible. Homogeneous networks improve the characteristics by replicating the same switching circuits so that more bits and words can be processed per second.

Charle R. Rupp

Papers

Reconfigurable computer architecture for use in signal processing applications

Toggle bus circuit

Reconfigurable computer component with adaptive logic processor

Bus transmitter-receiver system