Patent
Reconfigurable computer architecture for use in signal processing applications
TLDR
The Adaptive Logic Processor (ALP) as mentioned in this paper uses a programmable logic structure called an adaptive logic processor, similar to an extendible field programmable gate array (FPGA) and is optimized for the implementation of program specific pipeline functions.Abstract:
An architecture for information processing devices which allows the construction of low cost, high performance systems for specialized computing applications involving sensor data processing. The reconfigurable processor architecture of the invention uses a programmable logic structure called an Adaptive Logic Processor (ALP). This structure is similar to an extendible field programmable gate array (FPGA) and is optimized for the implementation of program specific pipeline functions, where the function may be changed any number of times during the progress of a computation. A Reconfigurable Pipeline Instruction Control (RPIC) unit is used for loading the pipeline functions into the ALP during the configuration process and coordinating the operations of the ALP with other information processing structures, such as memory, I/O devices, and arithmetic processing units. Multiple components having the reconfigurable architecture of the present invention may be combined to produce high performance parallel processing systems based on the Single Instruction Multiple Data (SIMD) architecture concept.read more
Citations
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Patent
Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
TL;DR: In this article, a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing is proposed, which includes a plurality of heterogeneous computational elements coupled to an interconnection network.
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High density semiconductor memory cell and memory array using a single transistor and having counter-doped poly and buried diffusion wordline
TL;DR: In this article, a programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed, where the transistor has its gate formed from the column bitlines and its source connected to the row wordlines.
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Reconfigurable computing architecture for providing pipelined data paths
TL;DR: In this article, the authors propose a reconfigurable data path that combines static and dynamic control information to reduce the amount of dynamic control used to achieve flexible operation by using a combination of dynamic and static control information.
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Reconfigurable integrated circuit
Graeme Roy Smith,Dyson Wilkes +1 more
TL;DR: In this paper, a reconfigurable integrated circuit is provided wherein the available hardware resources can be optimised for a particular application by dynamically reconfiguring (in both real-time and non-real-time) the available resources.
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Devices and methods with programmable logic and digital signal processing regions
TL;DR: A programmable logic integrated circuit device (PLD) includes a dedicated (i.e., at least part hard-wired) digital signal processing region for performing or at least helping to perform digital signal-processing tasks that are unduly inefficient to implement in the more general-purpose PLC and/or that, if implemented in the PLC, would operate too slowly as discussed by the authors.
References
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Patent
Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
TL;DR: In this article, an integrated circuit computing device is comprised of a dynamically configurable Field Programmable Gate Array (FPGA), which is configured to implement a RISC processor and a Reconfigurable Instruction Execution Unit.
Proceedings ArticleDOI
DPGA-coupled microprocessors: commodity ICs for the early 21st Century
TL;DR: It is noted how the tight integration of reconfigurable logic into the processor can overcome some of the major limitations of contemporary attached reconfiguring computer engines.
Patent
System and method for dynamically reconfiguring a programmable gate array
TL;DR: In this article, a PGA with a number of virtual logic cells in excess of actual physical logic cells is presented, where the programming words are selectively engaged such that multiple functions are performed by the logic cell within the PGA.
Patent
FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in response to those instructions
TL;DR: In this paper, the authors propose a processor-like device capable of performing the computations necessary to reconfigure the FPGAs in the array in accordance with the next algorithm to be performed.
Patent
Programmable logic module and architecture for field programmable gate array device
Khaled El Ayat,Gregory Bakker,Jung-Cheun Lien,William C. Plants,Sinan Kaptanoglu,Runip Gopisetty,King W. Chan,Marko Chew +7 more
TL;DR: In this article, a user-programmable gate array architecture with a plurality of horizontal and vertical general interconnect channels, each including plurality of interconnect conductors some of which may be segmented, is presented.