Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

Methods and systems for utilizing design data in combination with inspection data

Various methods and systems for determining a position of inspection data in design data space are provided. One computer-implemented method includes determining a centroid of an alignment target formed on a wafer using an image of the alignment target acquired by imaging the wafer. The method also includes aligning the centroid to a centroid of a geometrical shape describing the alignment target. In addition, the method includes assigning a design data space position of the centroid of the alignment target as a position of the centroid of the geometrical shape in the design data space. The method further includes determining a position of inspection data acquired for the wafer in the design data space based on the design data space position of the centroid of the alignment target.

Methods and systems for determining a position of inspection data in design data space

Ten years ago Model-Based OPC (MB-OPC) was a research project of questionable usefulness, seen possibly as a fix until the next generation stepper was available. Today MB-OPC is one of the key technologies enabling 90nm production. In that brief span many technological challenges were resolved to allow MB-OPC to be performed on full chip layout with manageable computer resources and turnaround times. As MB-OPC has transitioned from a research to a production activity, several organizational challenges have arisen. Defining the steps and procedures involved in creating OPC techfiles has been necessary to allow the increased workload to be shared. Testing and documenting the OPC recipes has become a necessary discipline to ensure quality and repeatability in manufacturing. In addition to the engineers who create the OPC recipes, we now also have Fab OPC Engineers to support OPC verification and continuous improvement activities. Furthermore, the OPC process, i.e. the modification of the layout to account for the manufacturing process, has provided a tantalizing link between the design, process development and yield engineering communities. The EDA framework appears to provide a common language, however we are just beginning to ask the right questions to allow us to unlock the potential that appears so close. The paper will begin with a historical overview of the development of MB-OPC and describe the seemingly overwhelming obstacles, both computational and in mask fabrication that had to be overcome. The second part of the paper will deal with some of the problems that have arisen as MB-OPC has become a critical technology for high volume production. The final part of the paper will discuss how MB-OPC has changed the way that Lithography, Integration and Design engineers interact. Some examples of design/process interaction will be given as well as a discussion of future developments.

Full-chip lithography simulation and design analysis: how OPC is changing IC design

Computer-implemented methods and systems for detecting defects in a reticle design pattern are provided. One computer-implemented method includes acquiring images of the reticle design pattern using a sensor disposed on a substrate arranged proximate to an image plane of an exposure system configured to perform a wafer printing process using the reticle design pattern. The images illustrate how the reticle design pattern will be projected on a wafer by the exposure system at different values of one or more parameters of the wafer printing process. The method also includes detecting defects in the reticle design pattern based on a comparison of two or more of the images corresponding to two or more of the different values.

Methods and systems for detecting defects in a reticle design pattern

Various computer-implemented methods are provided. One method for evaluating reticle layout data includes generating a simulated image using the reticle layout data as input to a model of a reticle manufacturing process. The simulated image illustrates how features of the reticle layout data will be formed on a reticle by the reticle manufacturing process. The method also includes determining manufacturability of the reticle layout data using the simulated image. The manufacturability is a measure of how accurately the features will be formed on the reticle. Also provided are various carrier media that include program instructions executable on a computer system for performing a method for evaluating reticle layout data as described herein. In addition, systems configured to evaluate reticle layout data are provided. The systems include a computer system and a carrier medium that includes program instructions executable on the computer system for performing method(s) described herein.

Methods, systems, and carrier media for evaluating reticle layout data

A method and apparatus evaluates the runability of a photomask inspection tool that inspects plural sets of die, each die having a standard simulated industrial device feature at plural technology nodes. A technology node size is determined for each feature at which inspection by the tool provides no false detection of faults. A sensitivity module included on a photomask test plate along with a runability module allows determination of inspection tool sensitivity and runability in a single test sequence.

Method and apparatus for evaluating the runability of a photomask inspection tool

In the recent past significant work has been done to isolate and characterize suitable single layer Chemically Amplified Resist (CAR) systems for DUV printing applicable to photomask fabrication. This work is complicated by the inherent instability of most DUV CAR systems, particularly in air, showing unacceptable CD degradation over the normal photomask write time in today’s DUV mask pattern generators. The high reflectivity of most photomask substrates at DUV wavelengths, creating unacceptable standing waves in the photo resist profile, further compounds this problem. A single layer CAR system suitable for 90nm technology node mask fabrication with DUV printing has been characterized and optimized. Results of this optimization in terms of relevant mask making parameters will be detailed. Furthermore, comparison of the properties of this resist system to other commercially available systems, including FEP-171, will be shown. The pattern fidelity of DUV laser generated masks has been studied in considerable detail. A demonstration of the capabilities of the Etec Systems ALTA 4300 will be shown. The pattern fidelity achieved will be compared/contrasted to that achieved with today’s leading edge 50KeV vector scan e-beam systems. Advanced methods for modulating the DUV printed patterns’ fidelity will be detailed.
Finally, the cost and cycle time implications of inserting the DUV laser pattern generator into the mask manufacturing flow will be discussed.

DUV laser lithography for photomask fabrication

New reticle designs frequently contain mask features the inspection tools find objectionable. Typically these illegal features are handled in one of two ways. They are removed from the database with “do not inspect” regions, or the sensitivity is compromised to a level sufficient to reduce these nuisance defects to a tolerable level. Using the inspection machine to find these areas is both costly and inefficient. This paper presents a survey of the Manufacturing Rules Check option available from Transcription Enterprises to screen the database for these features before the reticle goes to inspection.

Using manufacturing rule check to prescreen reticle inspection databases

In the recent past Deep Ultra Violet (DUV) Laser generated photomasks have gained widespread acceptance for critical and semi-critical applications in semi-conductor lithography. The advent of stable, highly capable, single-layer Chemically Amplified Resist (CAR) processes has made fabrication of this type of mask very robust in today's mask manufacturing environment. This platform affords mask makers benefits of the highly parallel architecture available in today's DUV Laser pattern generators - providing excellent cost and cycle time advantages when compared with alternative leading-edge processes using 50 KeV VSB e-beam systems. To date literature on this topic has focused mostly on characterization and optimization of DUV mask making processes. Meanwhile treatment of the resultant aerial image for critical litho applications has been largely ignored. In this paper details of the aerial image produced using DUV Laser generated photomasks will be detailed. Both 248nm and 193nm source printing with multiple types of illumination will be discussed. Details of a print test comparison performed on photomasks from two popular mask lithography platforms in use today; DUV, and 50 KeV VSB, will be documented. Finally, the most recent process improvements achieved in DUV Laser mask fabrication will be detailed. Special attention will be given to the impact of these enhancements on image quality.

Imaging properties of a leading-edge DUV laser generated photomask

The Verimask inspection standard is widely used to qualify inspection systems due to its simplicity, ease of use in a production environment, and readily understandable defect sensitivity table. The Verimask's major drawback is that it does not characterize the runability of an inspection system. Runability refers to the system's ability to inspect various pattern types, a critical characteristic of inspection systems used for mask manufacturing. Comprehensive inspection system capability evaluation should include both sensitivity and runability tests. Other inspection test masks suffer the same shortcoming of Verimask, providing simple sensitivity analysis without runability evaluation. The Universal Inspection Standard was developed to expand the Verimask's sensitivity test and to provide a runability test. The UIS runability module contains several typical industrial feature types at multiple technology nodes. We have used UIS to evaluate and benchmark inspection system and algorithms. Future UIS versions will be available with different feature and defect types to keep pace with inspection system development. In short, UIS provides a means to quantify an inspection system's runability in addition to the traditional sensitivity evaluation.

Charles H. Howard

Papers

Method and apparatus for evaluating the runability of a photomask inspection tool

DUV laser lithography for photomask fabrication

Using manufacturing rule check to prescreen reticle inspection databases

Imaging properties of a leading-edge DUV laser generated photomask

Universal inspection standard for evaluation of inspection system and algorithm sensitivity and runability