A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Flash EEprom system

Certain embodiments described herein include a memory system which can communicate with a host system such as a disk controller of a computer system. The memory system can include volatile and non-volatile memory and a controller which are configured such that the controller backs up the volatile memory using the non-volatile memory in the event of a trigger condition. In order to power the system in the event of a power failure or reduction, the memory system can include a secondary power source which is not a battery and may include, for example, a capacitor or capacitor array. The memory system can be configured such that the operation of the volatile memory is not adversely affected by the non-volatile memory or the controller when the volatile memory is interacting with the host system.

Non-volatile memory module

A die 810 has an outer, annular via 814 filled with conductive material in order to electrically shield an inner via 816. A die 820 can be electrically shielded from another area 822 by use of a wall 823 having a trench with oxidized side walls and a conductive filling.

Intergrated circuit with coaxial isolation and method

Devices and methods are provided with respect to a gate stack for a nonvolatile structure. According to one aspect, a gate stack is provided. One embodiment of the gate stack includes a tunnel medium, a high K charge blocking and charge storing medium, and an injector medium. The high K charge blocking and charge storing medium is disposed on the tunnel medium. The injector medium is operably disposed with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling. According to one embodiment, the injector medium is disposed on the high K charge blocking and charge storing medium. According to one embodiment, the tunnel medium is disposed on the injector medium. Other aspects and embodiments are provided herein.

Scalable flash/NV structures and devices with extended endurance

Structures and methods for Flash memory with low tunnel barrier intergate insulators are provided. The non-volatile memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al2O3, Ta2O5, TiO2, ZrO2, and Nb2O5. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

Flash memory with low tunnel barrier interpoly insulators

A dynamic random access memory having a non-volatile back-up storage capability including a latent image capability, and method of operating the memory. Each memory cell is composed of a dynamic portion and a non-volatile portion connected to the dynamic portion. The non-volatile portion is formed of a dual gate FET, one gate of which is a floating gate. A segment of DEIS (Dual Electron Injection Structure) material is provided to control the charge of the floating gate. A capacitor couples the floating gate to the source of the dual gate FET and to the data node of the cell. The second gate of the dual gate FET can be grounded to turn off the channel of the dual gate FET independent of the charge on the floating gate during normal dynamic memory operations. To perform a non-volatile storing operation, the voltage applied to the DEIS material opposite the floating gate is taken first positive and then negative. During the positive portion of the cycle, if the data at the data node is a data 0, a positive charge is stored on the floating gate, while if the data at the data node is a data 0, a positive charge is stored on the floating gate during the negative portion of the cycle. To restore the data, a data 1 is written at the data node and the second gate of the dual gate FET transistor is pulsed to thereby allow the charge stored on the floating gate to control the conductivity of the channel of the dual gate FET. If a positive charge is stored on the floating gate, the channel conducts and discharges the data node, while if a negative charge is stored on the floating gate, the channel remains non-conductive and the charge at the data node is retained.

Dynamic RAM with non-volatile back-up storage and method of operation thereof

Components of an Ethernet communication system are placed in low power modes when such low power modes are feasible and permitted. The auto-negotiation next page feature of the Ethernet standard is utilized to exchange signals indicating that both ends of the system are capable of a low power mode. If capable and conditions for low system power usage permit, then the auto-negotiation feature is used to signal the eligibility of both ends of the system to enter a low power mode at which time the low power mode is activated. The system remains in the low power mode until data is to be transmitted.

Power conservation in communication systems

An adaptive equalization and regeneration system is provided for accurately reconstructing a received data pulse train which has been degraded with respect to amplitude and instantaneous frequency. The system comprises an equalizer which responds to a control signal to provide a variable gain function for the received signal and output an equalized signal, digital phase lock logic for receiving and extracting timing information from the equalized signal, a regenerator for matching the timing information with the equalized signal to reconstruct the received data in its originally transmitted form, and control circuitry for providing the control signal to the equalizer. The control signal adjusts the slope of the equalizer gain function so as to minimize amplitude and instantaneous frequency degradation at the equalizer output. The system includes a mechanism to detect and calculate total signal degradation at the equalizer output. Control logic is used to identify the slope of the equalizer gain function at which total signal degradation is minimized. The control signal, which corresponds to this identified slope, is applied to the equalizer in real time to maintain minimum total signal degradation at the equalizer output.

Adaptive equalization and regeneration system

In the electrically alterable read only memory cell a reduction in cell area and an improvement in tolerance allowed for programming and erase voltages is achieved utilizing a diffused control gate (3) having improved capacitive coupling to the floating gate (7) through a thin oxide layer (5) grown on single crystal silicon (1). A thin oxide layer (6) is also grown over the channel area (2). Polyoxide layers (8) and (10) isolate the programming gate (9) from the floating gate (7) and the latter from the erase gate (11). The ratio of thickness between the oxide layers (5) and (6) and the polyoxide layers (8) and (10) is of one to four or five.

Electrically alterable read only memory cell

A phase lock loop circuit (PLL) is manufactured as a part of each very large scale integrated circuit (VLSI) that might need clock pulses. When these VLSI chips are mounted on a printed circuit board (PC), three crystal oscillators are also mounted on the PC in order to provide redundancy. In order to identify crystal oscillators that are less desirable from the standpoint of operation and accuracy, a circuit is mounted on the PC for comparing oscillator frequencies and detecting when lack of frequency agreement is noted. A gating circuit receives the output of the detecting circuit for selecting and passing clock pulses only from a properly functioning crystal oscillator to the rest of the PC. Programmable counters are provided in the PLLs to allow local generation within each VLSI of clock pulses at a frequency that is a ratio of the frequency of the crystal-generated clock pulses that are circulated throughout the PC.

Charles Reeves Hoffman

Papers

Dynamic RAM with non-volatile back-up storage and method of operation thereof

Power conservation in communication systems

Adaptive equalization and regeneration system

Electrically alterable read only memory cell

Reliable clock source having a plurality of redundant oscillators