The invention relates to a single event transient disturbance reinforced latch circuit and belongs to the field of circuit design. The single event transient disturbance reinforced latch circuit comprises a first lowpass filter unit and a latch. First way data input of a data input end is connected with a first input end of the latch. Second data input of the data input end is connected with a second input end of the latch through the first lowpass filter unit. The first lowpass filter unit is a circuit unit which is composed of a passive device and is used for removing a high-frequency signal. The first lowpass filter unit for removing the high-frequency signal is composed of the passive device, the filter capacity only needs to be greater than the maximum pulse width produced by single event transient disturbance, the working frequency of the latch circuit is not influenced, and a circuit structure is simple. The passive device itself does not produce the single event transient disturbance and an area and the power consumption of a storage unit are not increased, so the single event effect resistance of logic circuits such as the latch and a trigger can be effectively improved.

Single event transient disturbance reinforced latch circuit

The invention belongs to the technical field of D flip-flops, and provides an asynchronous reset D flip-flop with the capacity for resisting single event upset. The D flip-flop comprises a clock signal input circuit, a reset signal input circuit, a main latch buffering circuit, an auxiliary latch buffering circuit, a main latch and an auxiliary latch, and the main latch and the auxiliary latch are latches with bimodule redundancy reinforcing. Compared with the prior art, the buffering circuits are additionally arranged before the main latch and the auxiliary latch, the capacity for resisting single event upset of the asynchronous reset D flip-flop is improved, bimodule redundancy reinforcing is carried out on the main latch and the auxiliary latch, namely the main latch and the auxiliary latch are separated into a pull-up PMOS tube and a pull-down NMOS tube redundant to each other in the C2MOS circuits, a feedback loop possibly caused by single particle transient pulse in the auxiliary latch is avoided, the C2MOS circuits in the main latch and the auxiliary latch are improved, control over the circuits by clock signals is achieved through a CMOS transmission gate, and the capacity for resisting single event upset of the asynchronous reset D flip-flop is improved further.

Asynchronous reset D flip-flop with capacity for resisting single event upset

The invention discloses a dual-clock anti-single-particle latch circuit. The circuit possesses two clock input signals. Two completely-same clock signals are used to control a data logic circuit and astorage structure possessing a redundancy node respectively. When a single particle transient event is generated in a unit, a single particle overturn event can be ensured not to be generated. For the single particle transient event generating in a unit external chip clock network, a pair of filters can be implemented on the clock network to drive the clock tree structure of the multiple dual-clock anti-single-particle latches so as to eliminate a single-particle transient pulse from a unit external clock network. In the invention, the probability of generating the single particle transient pulses on any clock nodes inside and outside the unit and on multiple clock nodes can be effectively reduced; through applying the integrated circuit of the latch, the introduction number of anti-single-particle transient reinforcement circuits (the number of transistors) is much less than a traditional reinforcement design; and the circuit possesses characteristics of low power consumption, a fastspeed, a small area and low cost.

Dual-clock anti-single-particle latch

The invention discloses a well potential measurement circuit under single particle effect modulation in a CMOS process. The well potential measurement circuit comprises an acquisition module which collects M well contact potential values, a D trigger module corresponding to N different clock signals CLK, and a PISO output module. The space position precision is controlled through collecting the well potential values of different positions, and the numerical precision of measuring the well potentials is controlled through the difference of the turn thresholds of an NAND gate in the acquisition module. On the basis of multiple first-level time control D trigger sub modules controlled by different clock signals, the time precision of measuring the well potential is set through controlling the clock signal of each sub module, and thus the numerical distribution measurement of the well potential of single particle effect modulation in time and space is realized. The circuit is suitable for the measurement of an N well in a P type substrate under the single particle effect modulation and the measurement of a P well in an N type substrate under the single particle effect modulation.

Well potential measurement circuit under single particle effect modulation in CMOS process

A delay flip-flop comprises a clock module, a delay filtering module, a master-slave DICE latch module and an output module, wherein the master-slave DICE latch module outputs a corresponding data signal to the data output module according to a clock signal that is output from the clock module and an outer data signal that is received through the delay filtering module. The master-slave DICE latch module is composed of a master-grade module and a slave-grade module. The delay filtering module is used for preventing entering of a transient pulse which is caused by a single event effect into the register. The master-slave DICE latch module is used for correcting inner node upset which is caused by the single-particle effect. The delay filtering module performs a function of preventing a single event transient pulse. The master-slave DICE latch module prevents overturning of an inner storage node, thereby performing a function of preventing single event upset. A protective belt structure is added in layout design. The structure of the delay flip-flop effectively restrains single event latchup, and facilitates reduction of a single event transient pulse width in a circuit.

Chen Zhi

Papers

Delay flip-flop