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Patent

Delay flip-flop

Chen Zhi, +1 more
TLDR
In this article, a delay flip-flop consisting of a clock module, delay filtering module, a master-slave DICE latch module and an output module is used for correcting inner node upset caused by the single-particle effect.
Abstract
A delay flip-flop comprises a clock module, a delay filtering module, a master-slave DICE latch module and an output module, wherein the master-slave DICE latch module outputs a corresponding data signal to the data output module according to a clock signal that is output from the clock module and an outer data signal that is received through the delay filtering module. The master-slave DICE latch module is composed of a master-grade module and a slave-grade module. The delay filtering module is used for preventing entering of a transient pulse which is caused by a single event effect into the register. The master-slave DICE latch module is used for correcting inner node upset which is caused by the single-particle effect. The delay filtering module performs a function of preventing a single event transient pulse. The master-slave DICE latch module prevents overturning of an inner storage node, thereby performing a function of preventing single event upset. A protective belt structure is added in layout design. The structure of the delay flip-flop effectively restrains single event latchup, and facilitates reduction of a single event transient pulse width in a circuit.

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Citations
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TL;DR: In this article, a single event transient disturbance reinforced latch circuit is proposed, which consists of a first lowpass filter unit and a latch, which is used for removing a high-frequency signal.
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TL;DR: In this paper, an asynchronous reset D flip-flop with the capacity to resist single event upsets was presented, where the buffering circuits were additionally arranged before the main latch and the auxiliary latch, and the capacity for resisting single event upset was improved.
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TL;DR: In this article, a dual-clock anti-single-particle latch circuit is proposed to eliminate a single particle transient pulse from a unit external clock network, where two completely same clock signals are used to control a data logic circuit and astorage structure possessing a redundancy node respectively.
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TL;DR: In this article, a well potential measurement circuit under single particle effect modulation in a CMOS process is presented, which is suitable for the measurement of an N well in a P type substrate under the single-particle effect modulation.
References
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Method and apparatus for reducing radiation and cross-talk induced data errors

TL;DR: In this paper, the authors provide an integrated circuit comprising of a number of latches and filters, each of which is connected to a corresponding storage node in the plurality of storage nodes.
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TL;DR: In this paper, the first scrub circuit is configured to access in a sequence each of the first plurality of data groups to correct any detected errors in read from the first memory array.
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TL;DR: In this paper, a single-event-upset resistant resettable scan structure D trigger is presented, which is used in the fields of aviation, space flight and the like.