Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct but temporally aligned data and clocking signals over the same transport medium. Embodiments providing enhanced LPDDR interfaces are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.

Orthogonal differential vector signaling codes with embedded clock

A data receiver implemented in an integrated circuit is described. The data receiver comprises an input receiving a data signal; a first equalization circuit coupled to receive the data signal, wherein the first equalization circuit is used to receive the data of the data signal; and a second equalization circuit coupled to receive the data signal, wherein the second equalization circuit is used to adjust a clock phase offset.

Data receivers and methods of implementing data receivers in an integrated circuit

Described is an apparatus which comprises: a Variable Gain Amplifier (VGA); a set of samplers to sample data output from the VGA according to a clock signal; and a Clock Data Recovery (CDR) circuit to adjust phase of the clock signal such that magnitude of a first post-cursor signal associated with the sampled data is substantially half of a magnitude of a primary cursor tap associated with the sampled data.

Low power high speed receiver with reduced decision feedback equalizer samplers

Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

High performance phase locked loop

Methods and systems are described for generating, using a voltage-controlled oscillator (VCO), a plurality of phases of a local clock signal, generating a phase-error signal using a phase comparator receive a phase of the local clock signal and a reference clock signal, and configured to output the phase-error signal, generating a frequency-lock assist (FLA) signal using a FLA circuit receiving one or more phases of the local clock signal and the reference clock signal, the FLA signal indicative of a magnitude of a frequency error between the reference clock signal and the local clock signal, and generating a VCO control signal using an error accumulator circuit receiving the phase-error signal and the FLA signal, and responsively providing the VCO control signal to the VCO to lock the local clock signal to the reference clock signal

Lock detector for phase lock loop

In one embodiment, a differential amplifier (130) is provided. Gates of a first differential pair of transistors (132/134), of a first conductivity type, and a second pair or transistors (146/148), of a second conductivity type are coupled to first and second input terminals of the differential amplifier. A first pair of adjustable current sources (136/138) are configured to adjust respective tail currents of the first differential pair of transistors in response to a first bias current control signal. A second pair of adjustable current sources (152/154) are configured to adjust respective tail currents of the second differential pair of transistors in response to the first bias current control signal. A third pair of adjustable current sources (142/144) are configured to adjust respective currents through the second differential pair of transistors in response to a second bias current control signal.

Cheng-Hsiang Hsieh

Papers

Data receivers and methods of implementing data receivers in an integrated circuit

Receiver having a wide common mode input range