Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct but temporally aligned data and clocking signals over the same transport medium. Embodiments providing enhanced LPDDR interfaces are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.

Orthogonal differential vector signaling codes with embedded clock

Described is an apparatus which comprises: a Variable Gain Amplifier (VGA); a set of samplers to sample data output from the VGA according to a clock signal; and a Clock Data Recovery (CDR) circuit to adjust phase of the clock signal such that magnitude of a first post-cursor signal associated with the sampled data is substantially half of a magnitude of a primary cursor tap associated with the sampled data.

Low power high speed receiver with reduced decision feedback equalizer samplers

Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

High performance phase locked loop

An injection-locked phase-locked loop (ILPLL) circuit includes a delay-locked loop (DLL) and an ILPLL. The DLL is configured to generate a DLL clock by performing a delay-locked operation on a reference clock. The ILPLL includes a voltage-controlled oscillator (VCO), and is configured to generate an output clock by performing an injection synchronous phase-locked operation on the reference clock. The DLL clock is injected into the VCO as an injection clock of the VCO.

Injection-locked phase locked loop circuits using delay locked loops

Methods and systems are described for generating, using a voltage-controlled oscillator (VCO), a plurality of phases of a local clock signal, generating a phase-error signal using a phase comparator receive a phase of the local clock signal and a reference clock signal, and configured to output the phase-error signal, generating a frequency-lock assist (FLA) signal using a FLA circuit receiving one or more phases of the local clock signal and the reference clock signal, the FLA signal indicative of a magnitude of a frequency error between the reference clock signal and the local clock signal, and generating a VCO control signal using an error accumulator circuit receiving the phase-error signal and the FLA signal, and responsively providing the VCO control signal to the VCO to lock the local clock signal to the reference clock signal

Lock detector for phase lock loop

A data receiver implemented in an integrated circuit is described. The data receiver comprises an input receiving a data signal; a first equalization circuit coupled to receive the data signal, wherein the first equalization circuit is used to receive the data of the data signal; and a second equalization circuit coupled to receive the data signal, wherein the second equalization circuit is used to adjust a clock phase offset.

Data receivers and methods of implementing data receivers in an integrated circuit

An apparatus relates generally to an injection-controlled-locked phase-locked loop (“ICL-PLL”) is disclosed. In this apparatus, a delay-locked loop is coupled to an injection-locked phase-locked loop. An injection-locked oscillator of the injection-locked phase-locked loop is in a feedback loop path of the delay-locked loop.

Injection-controlled-locked phase-locked loop

An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data clock signal and a crossing clock signal, respectively, which are derived from a sampling clock signal; adjusting a phase of the sampling clock signal using a clock and data recovery (CDR) circuit based on the data samples and the crossing samples; adjusting relative phase between the data clock signal and the crossing clock signal from a first phase difference to a second phase difference that is less than ninety degrees; and reverting the relative phase between the data clock signal and the crossing clock signal to the first phase difference after a threshold time period.

Temporal change in data-crossing clock phase difference to resolve meta-stability in a clock and data recovery circuit

An apparatus includes a decision feedback equalizer (FIG. 2, 206; FIG. 4, 206) configured to receive a parallel signal (FIG. 4, 214) generated based on a first clock (FIG. 3, ADC OUTPUT CLOCK). The decision feedback equalizer includes a first equalization block (FIG. 4, [DFE[0]] configured to receive a first symbol (FIG.3, ADC[0]) of a first set of parallel symbols (FIG. 3, ADC[0:N-1 ]) provided by the parallel signal during a first clock cycle [FIG. 3, 306] of the first clock. A decision feedback equalization is performed by the first equalization block to the first symbol to provide a first decision (FIG. 4, 422, D[0]) to a second equalization block. The second equalization block (FIG. 4, DFE[1 ]) is configured to receive a second symbol (FIG.3, ADC[1 ]) of the first set of parallel symbols and perform a decision feedback equalization to the second symbol using the first decision received from the first equalization block to provide a second decision (FIG. 4, 422, D[1 ]) during the first clock cycle.

Decision feedback equalizer

A driver circuit includes a plurality of output circuits (208) coupled in parallel between a differential input (Inn, Inp) and a differential output (Txn, Txp) and having a first common node (V refP ) and a second common node (V refn ). Each of the plurality of output circuits includes a series combination of a pair of inverters (M p1 , M P2 and M n1 , M n2 ) and a pair of resistors (R p , R n ), coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator (210 1 ) having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator (210 2 ) having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit (206) coupled between the outputs of the first voltage regulator and the second voltage regulator.

Kun-Yung Chang

Papers

Data receivers and methods of implementing data receivers in an integrated circuit

Injection-controlled-locked phase-locked loop

Temporal change in data-crossing clock phase difference to resolve meta-stability in a clock and data recovery circuit

Decision feedback equalizer

Impedance and swing control for voltage-mode driver