The System-On-Chip (SoC) revolution challenges both design and test engineers, especially in the area of power dissipation. Generally, a circuit or system consumes more power in test mode than in normal mode. This extra power consumption can give rise to severe hazards in circuit reliability or, in some cases, can provoke instant circuit damage. Moreover, it can create problems such as increased product cost, difficulty in performance verification, reduced autonomy of portable systems, and decrease of overall yield. Low power dissipation during test application is becoming increasingly important in today's VLSI systems design and is a major goal in the future development of VLSI design.

/pdf/survey-of-low-power-testing-of-vlsi-circuits-1fqu92r1r6.pdf

Survey of low power testing of VLSI circuits

Homogeneous manycore systems are emerging for tera-scale computation and typically utilize Network-on-Chip (NoC) as the communication scheme between embedded cores. Effective defect tolerance techniques are essential to improve the yield of such complex integrated circuits. We propose to achieve fault tolerance by employing redundancy at the core-level instead of at the microarchitecture level. When faulty cores exist on-chip in this architecture, however, the physical topologies of various manufactured chips can be significantly different. How to reconfigure the system with the most effective NoC topology is a relevant research problem. In this paper, we first show that this problem is an instance of a well known NP-complete problem. We then present novel solutions for the above problem, which not only maximize the performance of the on-chip communication scheme, but also provide a unified topology to Operating System and application software running on the processor. Experimental results show the effectiveness of the proposed techniques.

/pdf/on-topology-reconfiguration-for-defect-tolerant-noc-based-2xrvn8atf2.pdf

On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems

A new X-tolerant multiple-input signature register (MISR) compaction methodology is proposed which can compact output streams containing unknown (X) values. Unlike conventional X-masking approaches, it does not require any masking logic at the input of the MISR. Instead it uses symbolic simulation to express each bit of the MISR signature as a linear equation in terms of the X's. Linearly dependent combinations of the signature bits are identified with Gaussian elimination and XORed together using a programmable XOR to cancel out all X values thereby yielding deterministic values that are invariant of what the final values of the X's end up being during the test. These X-canceled values can be compacted in a separate MISR to generate a final X-free signature. Each intermediate signature for an m-bit MISR can tolerate k X's present anywhere in the output stream with error detection capability equivalent to using an m-k bit MISR with no unknowns. The tester storage requirement is a small constant times the total number of unknowns in the test set and thus does not depend on the scan architecture, the number of test vectors, or the distribution of X's which is a key advantage compared with other X-tolerant compaction schemes.

https://users.ece.utexas.edu/~touba/research/itc07.pdf

X-canceling MISR — An X-tolerant methodology for compacting output responses with unknowns using a MISR

Fault Tolerance - On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems

Cryptographic circuits need to be protected against side-channel attacks, which target their physical attributes while the cryptographic algorithm is in execution. There can be various side-channels, such as power, timing, electromagnetic radiation, fault response, and so on. One such important side-channel is the design-for-testability (DfT) infrastructure present for effective and timely testing of VLSI circuits. The attacker can extract secret information stored on the chip by scanning out test responses against some chosen plaintext inputs. The purpose of this paper is to first present a detailed survey on the state-of-the-art in scan-based side-channel attacks on symmetric and public-key cryptographic hardware implementations, both in the absence and presence of advanced DfT structures, such as test compression and X-masking, which may make the attack difficult. Then, the existing scan attack countermeasures are evaluated for determining their security against known scan attacks. In addition, JTAG vulnerability and security countermeasures are also analyzed as part of the external test interface. A comparative area-timing-security analysis of existing countermeasures at various abstraction levels is presented in order to help an embedded security designer make an informed choice for his intended application.

https://securewww.esat.kuleuven.be/cosic/publications/article-2416.pdf

Cheng Wen Wu

Papers

VLSI Test Principles and Architectures