An apparatus may include a semiconductor chip and a fluidics assembly. The semiconductor chip has an array of wells and an array of sensors and each sensor of the array of sensors is in fluid communication with a well of the array of wells. The fluidics assembly is located on top of the semiconductor chip and is configured to deliver fluids to the semiconductor chip. The fluidics assembly includes a flow expansion chamber configured to introduce the fluids, an outlet portion configured to pipe out the fluids, and a flow chamber portion. The flow chamber portion is configured to allow the fluids to flow from the flow expansion chamber to the outlet portion and to allow the fluids to interact along the way with material in the array of wells. The flow expansion chamber has a curved wall at the top or bottom so that the height of the flow expansion chamber at the center is less than at the walls that restrict the fluids to the left and right.

Methods and apparatus for measuring analytes using large scale fet arrays

Methods and apparatuses relating to large scale FET arrays for analyte detection and measurement are provided. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes.

Methods and apparatus for detecting molecular interactions using FET arrays

In one aspect there is provided a method. The method may include receiving a first analog radio frequency signal including a signal of interest and an interference signal caused by a second analog radio frequency signal transmitted in full duplex over a channel from which the first analog transmission is received; combining the first analog radio frequency signal and a portion of the second analog radio frequency signal to generate an output analog radio frequency signal characterized by at least a reduction or an elimination of the interference signal included in the output analog radio frequency signal; and providing the output analog radio frequency signal. Related apparatus, systems, methods, and articles are also described.

Single channel full duplex wireless communications

https://www.it.uu.se/edu/course/homepage/projektDV/ht14/NetInfArch-elsevier-published.pdf

Network of Information (NetInf) - An information-centric networking architecture

A first user equipment (UE) and a second UE communicate with a network element (e.g., an eNB) over a carrier (e.g., an uplink or downlink cellular carrier). The first and second UEs also engage in D2D communication using resources of the carrier that have been allocated to them by the network entity. Using the allocated resources, the first and second UEs communicate using a subframe that has a first set of symbols in during which the first UE transmits, a second set of symbols during which the second UE transmits, and a guard interval between the first and second UEs.

Method and apparatus for device-to-device communication

Frequenzabhängige i/q-ungleichgewichtsschätzung

The invention proposes a way of inserting an analog test signal during normal reception into analog blocks of an OFDM receiver in such a way that the reception is either not corrupted at all, or only very little. This is achieved either by inserting the analog test signal in time or frequency where it does not corrupt the received signal, or by accounting for the interfering analog test signal in the decoding process.

Test signal in an OFDM receiver

A system simulator is proposed and developed, which can help to optimize design parameters and hence minimize the number of collisions. In order to search the optimal design parameter combination which meets the user requirement, the proposed simulator has some knobs: partitioning between software and hardware, scheduling the operations in the system, and memory merging, all of which can be adjusted to predict collisions and search the optimal architecture. Also, design parameters can be adjusted sequentially to cover all design options and estimate the predicted performance for each option. The proposed system simulator is evaluated with an example signal processing algorithm, orthogonal matching pursuit (OMP) algorithm. Performances of four cases of the OMP algorithm are predicted by the proposed simulator and in turn are compared with the actual performances on ZedBoard. The proposed simulator can predict the performance of heterogeneous systems on chips with under 5% error for all the candidate architectures for OMP while taking the system bus and memory conflicts into account. Moreover, the optimized heterogeneous SoC architecture for the OMP algorithm improves performance by up to 32% compared with the conventional CAG-based approach. The proposed simulator is verified that the proposed performance estimation algorithm is generally applicable to estimate the performance of any heterogeneous SoC architecture. For example, the estimation error is measured to be no more than 5.9% for the convolutional layers of CNNs and no more than 5.6% for the LDPC-coded MIMO-OFDM. In addition, the optimized heterogeneous SoC architecture improves performance by up to 48% for the third convolutional layer of AlexNet and 56% for the LDPC-coded MIMO-OFDM. Lastly, compared with the conventional simulation-based approaches, the proposed estimation algorithm provides a speedup of one to two orders of magnitudes. The source code is available on the GitHub repository: https://github.com/SDL-KU/HetSoCopt.

Modeling and Simulation of System Bus and Memory Collisions in Heterogeneous SoCs

All-digital phase-locked loops (ADPLLs) based on the time-to-digital converter (TDC) and the frequency discriminator (FD) are modeled and analyzed in terms of quantization effects. Using linear models with quantization noise sources, theoretical analysis and simulation are carried out to obtain the output phase noise of each building block of the TDC-based ADPLL. It is newly derived that the TDC noise component caused by the delta-sigma modulator (DSM) and the finite resolution of the digitally controlled oscillator is not white. Namely, the in-band phase noise caused by the DSM-induced TDC is not white, which is due to the integrate-and-dump and subsampling operations of the TDC. This can give some insight into the design of low-noise ADPLLs. Some structures of delta-sigma FDs, which can serve as an alternative to the TDC, are also newly analyzed in terms of quantization noise, using the derived linear noise model.

Quantization Noise Analysis of Time-to-Digital-Converter-Based All-Digital Phase-Locked Loop and Frequency Discriminators

In this letter, IQ mismatch of a CA-supporting terminal for LTE-A is analyzed and each of the analog blocks is modeled mathematically. Based on the model, a new digital calibration algorithm is proposed and verified using simulation results.

/pdf/digital-calibration-based-on-iq-mismatch-model-for-lte-a-ca-2yc9y37al5.pdf

Chester Park

Papers

Frequenzabhängige i/q-ungleichgewichtsschätzung

Test signal in an OFDM receiver

Modeling and Simulation of System Bus and Memory Collisions in Heterogeneous SoCs

Quantization Noise Analysis of Time-to-Digital-Converter-Based All-Digital Phase-Locked Loop and Frequency Discriminators

Digital Calibration Based on IQ Mismatch Model for LTE-A CA-Supporting Transceivers