An apparatus may include a semiconductor chip and a fluidics assembly. The semiconductor chip has an array of wells and an array of sensors and each sensor of the array of sensors is in fluid communication with a well of the array of wells. The fluidics assembly is located on top of the semiconductor chip and is configured to deliver fluids to the semiconductor chip. The fluidics assembly includes a flow expansion chamber configured to introduce the fluids, an outlet portion configured to pipe out the fluids, and a flow chamber portion. The flow chamber portion is configured to allow the fluids to flow from the flow expansion chamber to the outlet portion and to allow the fluids to interact along the way with material in the array of wells. The flow expansion chamber has a curved wall at the top or bottom so that the height of the flow expansion chamber at the center is less than at the walls that restrict the fluids to the left and right.

Methods and apparatus for measuring analytes using large scale fet arrays

Methods and apparatuses relating to large scale FET arrays for analyte detection and measurement are provided. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes.

Methods and apparatus for detecting molecular interactions using FET arrays

In one aspect there is provided a method. The method may include receiving a first analog radio frequency signal including a signal of interest and an interference signal caused by a second analog radio frequency signal transmitted in full duplex over a channel from which the first analog transmission is received; combining the first analog radio frequency signal and a portion of the second analog radio frequency signal to generate an output analog radio frequency signal characterized by at least a reduction or an elimination of the interference signal included in the output analog radio frequency signal; and providing the output analog radio frequency signal. Related apparatus, systems, methods, and articles are also described.

Single channel full duplex wireless communications

https://www.it.uu.se/edu/course/homepage/projektDV/ht14/NetInfArch-elsevier-published.pdf

Network of Information (NetInf) - An information-centric networking architecture

A first user equipment (UE) and a second UE communicate with a network element (e.g., an eNB) over a carrier (e.g., an uplink or downlink cellular carrier). The first and second UEs also engage in D2D communication using resources of the carrier that have been allocated to them by the network entity. Using the allocated resources, the first and second UEs communicate using a subframe that has a first set of symbols in during which the first UE transmits, a second set of symbols during which the second UE transmits, and a guard interval between the first and second UEs.

Method and apparatus for device-to-device communication

Sparse convolutional neural network (SCNN) accelerators eliminate unnecessary computations and memory access by exploiting zero-valued activation pixels and filter weights. However, data movement between the multiplier array and accumulator buffer tends to be a performance bottleneck. Specifically, the scatter network, which is the core block of SCNN accelerators, delivers Cartesian products to the accumulator buffer, and certain products are not immediately delivered owing to bus contention. A previous SCNN-based architecture eliminates bus contention and improves the performance significantly by making use of different dataflows. However, it relies only on weight sparsity, and its performance is highly dependent on the workload. In this paper, we propose a novel scatter network architecture for SCNN accelerators. First, we propose network topologies (such as window and split queuing), which define the connection between the FIFOs and crossbar buses in the scatter network. Second, we investigate arbitration algorithms (such as fixed priority, round-robin, and longest-queue-first), which define the priorities of the products delivered to the accumulator buffer. However, the optimization of the scatter network architecture alone may not be able to provide sufficient performance gain since it does not help to reduce bus contention itself. In this paper, we propose a cubic-constrained bank allocation for the accumulator buffer, which reduces bus contention without any increase in the hardware area. Based on the results of cycle-accurate simulation, register-transfer-level (RTL) design, and logic synthesis, this study investigates the trade-off between the performance and complexity of SCNN accelerators. In detail, it is verified that, when the optimized SCNN accelerators are applied to AlexNet, the proposed scatter network architecture can remove most of the performance degradation due to bus contention, thereby improving the accelerator performance by 72%, with an area increase of 18%. It is also shown that the proposed bank allocation provides an additional performance gain of up to 31% when it is applied to SqueezeNet. The proposed scatter network architectures and bank allocation can eliminate bus contention in most Cartesian product-based accelerators, regardless of the workload, without changing accelerator components other than the scatter network.

Optimization of Scatter Network Architectures and Bank Allocations for Sparse CNN Accelerators

A decimation chain for multi-standard reconfigurable radios is presented for 900-MHz and 1,900-MHz dual-band cellular standards with a data interpolator based on the Lagrange method for adjusting the variable data rate to a fixed data rate appropriate for each standard. The two proposed configurations are analyzed and compared to provide insight into aliasing and the signal bandwidth by means of a newly introduced measure called interpolation error. The average interpolation error is reduced as the ratio of the sampling frequency to the signal BW is increased. The decimation chain and the multi-rate analogto-digital converter are simulated to compute the interpolation error and the output signal-to-noise ratio. Further, a method to operate the above-mentioned chain under a compressed mode of operation is proposed in order to guarantee continuous packet connectivity for inter-radio-access technologies. The presented decimation chain can be applied to LTE, WCDMA, GSM multi-mode multi-band digital front-end which will ultimately lead to the software-defined radio.

Decimation Chain Modeling for Dual-Band Radio Receiver and Its Operation for Continuous Packet Connectivity

A composite radio receiver back-end and digital front-end, made up of a delta-sigma analog-to-digital converter (ADC) with a high-speed low-noise sampling clock generator, and a fractional sample rate converter, are proposed and designed for a multi-mode reconfigurable radio. The proposed radio receiver architecture contributes to saving the chip area and thus lowering the design cost. To enable inter-radio access technology handover and ultimately software-defined radio reception, a reconfigurable radio receiver consisting of a multi-rate ADC with its sampling clock derived from a local oscillator (LO), followed by a rate-adjustable fractional sample rate converter for decimation, is designed. Clock phase noise and timing jitter are examined to support the effectiveness of the proposed radio receiver. A fractional sample rate converter is modeled and simulated with a cubic polynomial interpolator based on Lagrange method and its spectral-domain view is examined in order to verify its effect on al...

Reconfigurable radio receiver with fractional sample rate converter and multi-rate ADC based on LO-derived sampling clock

Methods of receiving multiple carriers using different RF mixer frequencies and related communications devices

A new system-level simulator, eF2lowSim, is proposed to estimate the bit-accurate and cycle-accurate performance of eFlash compute-in-memory (CIM) accelerators for convolutional neural networks. The eF2lowSim can predict the inference accuracy by considering the impact of circuit nonideality such as program disturbance. Moreover, the eF2lowSim can also evaluate the system-level performance of dataflow strategies that have a significant impact on hardware area and performance of eFlash CIM accelerators. The simulator helps to find the optimal dataflow strategy of an eFlash CIM accelerator for each convolutional layer. It is shown that the improvement of area efficiency amounts to 26.8%, 21.2% and 17.9% in the case of LeNet-5, VGG-9 and ResNet-18, respectively.

Chester Park

Papers

Optimization of Scatter Network Architectures and Bank Allocations for Sparse CNN Accelerators

Decimation Chain Modeling for Dual-Band Radio Receiver and Its Operation for Continuous Packet Connectivity

Reconfigurable radio receiver with fractional sample rate converter and multi-rate ADC based on LO-derived sampling clock

Methods of receiving multiple carriers using different RF mixer frequencies and related communications devices

eF2lowSim: System-Level Simulator of eFlash-Based Compute-in-Memory Accelerators for Convolutional Neural Networks