Internet of Medical Things (IoMT) can connect many medical imaging equipment to the medical information network to facilitate the process of diagnosing and treating doctors. As medical image contains sensitive information, it is of importance yet very challenging to safeguard the privacy or security of the patient. In this work, a deep-learning-based image encryption and decryption network (DeepEDN) is proposed to fulfill the process of encrypting and decrypting the medical image. Specifically, in DeepEDN, the cycle-generative adversarial network (Cycle-GAN) is employed as the main learning network to transfer the medical image from its original domain into the target domain. The target domain is regarded as “hidden factors” to guide the learning model for realizing the encryption. The encrypted image is restored to the original (plaintext) image through a reconstruction network to achieve image decryption. In order to facilitate the data mining directly from the privacy-protected environment, a region of interest (ROI)-mining network is proposed to extract the interesting object from the encrypted image. The proposed DeepEDN is evaluated on the chest X-ray data set. Extensive experimental results and security analysis show that the proposed method can achieve a high level of security with a good performance in efficiency.

DeepEDN: A Deep-Learning-Based Image Encryption and Decryption Network for Internet of Medical Things

By exploring different granularities of data-level and task-level parallelism, we map 16 implementations of an Advanced Encryption Standard (AES) cipher with both online and offline key expansion on a fine-grained many-core system. The smallest design utilizes only six cores for offline key expansion and eight cores for online key expansion, while the largest requires 107 and 137 cores, respectively. In comparison with published AES cipher implementations on general purpose processors, our design has 3.5-15.6 times higher throughput per unit of chip area and 8.2-18.1 times higher energy efficiency. Moreover, the design shows 2.0 times higher throughput than the TI DSP C6201, and 3.3 times higher throughput per unit of chip area and 2.9 times higher energy efficiency than the GeForce 8800 GTX.

Parallel AES Encryption Engines for Many-Core Processor Arrays

An ultra-high throughput and fully pipelined implementation of AES algorithm on FPGA

Technologies are provided in example embodiments for analyzing an encrypted network flow. The technologies include monitoring the encrypted network flow between a first node and a second node, the network flow initiated from the first node; duplicating the encrypted network flow to form a copy of the encrypted network flow; decrypting the copy of the encrypted network flow using a shared secret, the shared secret associated with the first node and the second node; and scanning the network flow copy for targeted data.

Encrypted data inspection in a network environment

In this article, a high-speed and highly restricted encryption algorithm is proposed to cipher high-definition (HD) images based on the modified advanced encryption standard (AES) algorithm. AES is a well-known block cipher algorithm and has several advantages, such as high-level security and implementation ability. However, AES has some drawbacks, including high computation costs, pattern appearance, and high hardware requirements. The aforementioned problems become more complex when the AES algorithm ciphers an image, especially HD images. Three modifications are proposed in this paper to improve AES algorithm performance through, decreasing the computation costs, decreasing the hardware requirements, and increasing the security level. First, modification was conducted using MixColumn transformation in 5 rounds instead of 10 rounds in the original AES-128 to decrease the encryption time. Security is enhanced by improving the key schedule operation by adding MixColumn transformation to this operation as second modification. In addition, to decrease the hardware requirements, S-box and Inv. S-box in the original AES are replaced by one simple S-box used for encryption and decryption in the proposed method. The proposed AES version conducts one of the ciphering modes to solve the appearance pattern problem. Experimental results indicate that the proposed modifications to the AES algorithm made the algorithm more compatible with HD image encryption.

High Definition Image Encryption Algorithm Based on AES Modification

Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput (over several tens Gbps). However, low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 156 slices and a throughput of 876 Mbps, which outperformed the best reported result of 648 Mbps throughput found in literature.

High throughput 32-bit AES implementation in FPGA

Hardware implementation of advanced encryption standard (AES) algorithm has been in intensive discussion since its first publication by National Institute of Standards and Technology (NIST) in 2000, especially in high throughput over 1 Giga bits per second (Gbps). However, the studies of low area, low power and low cost implementations, which usually have throughput less than 1 Gbps and use the datapath less than 32-bit, have been appearing recently in ASIC as well as in FPGA for wireless communication and embedded hardware application. This paper proposes a 32-bit datapath implementation in small Xilinx FPGA Chip (Spartan-3 XC3S200). It uses 148 slice, 11 block RAMs (BRAMs) and achieves the data stream of 647 Mega bits per second ( Mbps) at 287 MHz working frequency. It obtains 3.4 times improvement to the best known similar design in terms of ratio throughput per area (Throughput/Area), and 20% smaller in slice area.

Compact FPGA implementation of 32-bits AES algorithm using Block RAM

Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput over several tens Giga bit per second (Gbps). However, lower throughput and low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 110 slices which is the smallest design among the literature reports. This small core, suitable for inexpensive small size FPGA chip implementation, is embedded in Xilinx Spartan3E with MicroBlaze processor for image encryption/decryption applications.

Embedded a low area 32-bit AES for image encryption/decryption application

A 32-bit AES implementation is proposed in small Xilinx FPGA chip (Spartan-3 XC3S200). It uses 148 slices, 11 block RAMs (BRAMs) and achieves a throughput of 647 mega bits per second ( Mbps) at 278 MHz working frequency. It achieve 3 times improvement in throughput and 3.4 times increase to the best known similar design in throughput per area and 8% smaller in slices area. An 128-bit AES implementation in FPGA (Virtex-II XC2VP20) by parallel operations of four above 32-bit AES is also presented. Comparison to state-ofart AES cores indicates that the proposed folded designed achieves 4780 Mbps and 410 slices, which outperformed the most works by 200% in throughput and requires 20% less reconfigurable area, which results over 250% improvement in throughput/slice metric.

The FPGA Implementation of 128-bits AES AlgorithmBased on Four 32-bits Parallel Operation

An 8-bit data-path AES implementation was proposed recently by Tim Good [Tim Good, Mohammed Benaissa, "Very small FPGA application-specific instruction processor for AES", IEEE Trans. Circuit and System,vol. 53, no. 7, 2006.] as application-specific- instruction-processor (ASIP) for the increasing popular applications in PDA, wireless network and embedded devices. This paper proposes an 8-bit AES implementation design that keeps MixColumn and sequential controls for AES operation in the processing area while moving the circuit necessary for other operations such as Sbox, ShiftRow and KeyExpansion to Block RAMs (BRAMs) of Xilinx FPGA chip. Thus, it keeps the low resource area around 130 slices uses 4 BRAMs and achieves 27 Megabit per second (Mbps) throughput. Our design obtains approximately 12 times (1200%) increase in throughput with 8% increase in resource area comparing to the ASIP instruction set design approach of 8-bit AES processor proposed in 2006.

Chi-Jeng Chang

Papers

High throughput 32-bit AES implementation in FPGA

Compact FPGA implementation of 32-bits AES algorithm using Block RAM

Embedded a low area 32-bit AES for image encryption/decryption application

The FPGA Implementation of 128-bits AES AlgorithmBased on Four 32-bits Parallel Operation

8-bit AES FPGA Implementation using Block RAM