International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

The use of static random access memory (SRAM)-based field programmable gate arrays (FPGAs) in harsh radiation environments has grown in recent years. These types of programmable devices require special mitigation techniques targeting the configuration memory, the user logic, and the embedded RAM blocks. This article provides a comprehensive survey of the literature published in this rich research field during the past 10 years. Furthermore, it can also serve as a tutorial for space engineers, scientists, and decision makers who need an introduction to this topic.

/pdf/mitigation-of-radiation-effects-in-sram-based-fpgas-for-1si9ypvqs2.pdf

Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

SRAM-based FPGAs are in-field reconfigurable an unlimited number of times. This characteristic, together with their high performance and high logic density, proves to be very convenient for a number of ground and space level applications. One drawback of this technology is that it is susceptible to ionizing radiation, and this sensitivity increases with technology scaling. This is a first order concern for applications in harsh radiation environments, and starts to be a concern for high reliability ground applications. Several techniques exist for coping with radiation effects at user application. In order to be effective they need to be complemented with configuration memory scrubbing, which allows error mitigation and prevents failures due to error accumulation. Depending on the radiation environment and on the system dependability requirements, the configuration scrubber design can become more or less complex. This paper classifies and presents current and novel design methodologies and architectures for SRAM-based FPGAs, and in particular for Xilinx Virtex-4QV/5QV, configuration memory scrubbers.

/pdf/design-techniques-for-xilinx-virtex-fpga-configuration-27fwfomqdy.pdf

Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers

Homogeneous multiprocessor systems with reconfigurable area (also known as Reconfigurable Multiprocessor Systems) are emerging as a popular design choice in current and future technology nodes to meet the heterogeneous computing demand of a multitude of applications enabled on these platforms. Application specific mapping decisions on such a platform involve partitioning a given application into software tasks (executed on one or more of the general purpose processors, GPPs) and the hardware tasks (realized as dedicated hardware on the reconfigurable area) to optimize and/or satisfy design constraints such as reliability, performance and design cost. Improving the reliability considering transient faults by increasing the number of checkpoints negatively impacts the reliability considering permanent faults. This trade-off is ignored in all prior studies on task mapping and scheduling. This paper proposes an optimization technique to decide the optimal number of checkpoints for the software tasks which minimizes aging of the GPPs while maximizing the transient fault-tolerance of the overall platform (GPPs and the reconfigurable area) and satisfying design cost and performance. Experiments conducted with synthetic and real-life application task graphs (cyclic and acyclic) demonstrate that the proposed technique minimizes aging and improves the platform lifetime by an average 60% as compared to the existing transient fault-aware techniques. Further, a gradient-based heuristic is proposed to minimize the design space exploration time by upto 500× with less than 5% deviation from optimal solution.

Aging-aware hardware-software task partitioning for reliable reconfigurable multiprocessor systems

In this paper, we propose a self-adaptive FPGA-based, partially reconfigurable system for space missions in order to mitigate Single Event Upsets in the FPGA configuration and fabric. Dynamic reconfiguration is used here for an on-demand replication of modules in dependence of current and changing radiation levels. More precisely, the idea is to trigger a redundancy scheme such as Dual Modular Redundancy or Triple Modular Redundancy in response to a continuously monitored Single Event Upset rate measured inside the on-chip memories itself, e.g., any subset (even used) internal Block RAMs. Depending on the current radiation level, the minimal number of replicas is determined at runtime under the constraint that a required Safety Integrity Level for a module is ensured and configured accordingly. For signal processing applications it is shown that this autonomous adaption to the different solar conditions realizes a resource efficient mitigation. In our case study, we show that it is possible to triplicate the data throughput at the Solar Maximum condition (no flares) compared to a Triple Modular Redundancy implementation of a single module. We also show the decreasing Probability of Failures Per Hour by 2 × 104 at flare-enhanced conditions compared with a non-redundant system. Our work is a part of the In-Orbit Verification of the Heinrich Hertz communication satellite.

A Self-Adaptive SEU Mitigation System for FPGAs with an Internal Block RAM Radiation Particle Sensor

This paper presents a novel design flow for the implementation of digital systems onto SRAM-based FPGAs with soft error mitigation properties. Traditional fault detection/tolerance techniques are coupled with the device dynamic reconfiguration property to achieve soft error mitigation capabilities, and are applied to the single component, to groups of components or to the entire system, based on the most convenient trade-off with respect to a set of parameters. The design flow performs a two-steps multiobjective design space exploration, driven by a cost function taking into account resource utilization, area, and reconfiguration time. A floorplanning based on precise FPGA resource models is introduced to guarantee the feasibility of the hardened solution, identifying a convenient mapping onto the heterogeneous reconfigurable fabric. Experimental results show that the achieved solutions, aimed at achieving a prompt, "on demand” recovery when fault occurs, are characterized by a reduction in reconfiguration time that is higher than 80 percent, a significant improvement with respect to classical solutions.

A Novel Design Methodology for Implementing Reliability-Aware Systems on SRAM-Based FPGAs

This letter proposes a classification algorithm to discriminate between recoverable and not recoverable faults occurring in static random access memory (SRAM)-based field-programmable gate arrays (FPGAs), with the final aim of devising a methodology to enable the exploitation of these devices also in space applications, typically characterized by long mission times, where permanent faults become an issue. By starting from a characterization of the radiation effects and aging mechanisms, we define a controller able to classify such faults and consequently to apply the appropriate mitigation strategy.

Fault Classification for SRAM-Based FPGAs in the Space Environment for Fault Mitigation

The floor planning activity is a key step in the design of systems on FPGAs, but the approaches available today rarely consider both the constraints imposed by the heterogeneous distribution of the resources in the devices and the reconfiguration capabilities. In fact, current-generation FPGAs present a complex architecture, but also offer more sophisticated reconfiguration features. The proposed floor planner, based on an accurate model of the devices, takes into account all these elements and finds an optimal solution, suitable for reconfigurable designs.

Automated Resource-Aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA Systems

The design of embedded systems has rapidly changed during the last decade. It is possible to identify two main responsible factors: hardware/software codesign and dynamic reconfiguration. The work presented in this paper tries to investigate how to consider the reconfiguration as an explicit dimension in the design flow for embedded systems. This work addresses the challenge introduced by the partial dynamic reconfiguration trying to propose a novel design flow, using the CoDeveloper framework to speedup the design process. The proposed flow allows the designer to define his/her desired specification using an high level design language such as C. Finally, it provides results showing how the proposed flow can be used by the designer to have more information useful in making the correct decisions during the design of his/her embedded system.

A Novel Hardware/Software Codesign Methodology Based on Dynamic Reconfiguration with Impulse C and Codeveloper

This paper proposes the design of a controller managing the fault tolerance of multi-FPGA platforms, contributing to the creation of a reliable system featuring high flexibility and resource availability. A fault management strategy that exploits the devices' reconfiguration capabilities is proposed, the Reconfiguration Controller, focus of this paper, is the main component in charge of implementing such strategy. The innovative points raised by this work are 1) the identification of a distributed control architecture, allowing the avoidance of single points of failure, 2) the management of both recoverable and non-recoverable faults, and 3) the definition of an overall reliable multi-FPGA system.

Chiara Sandionigi

Papers

A Novel Design Methodology for Implementing Reliability-Aware Systems on SRAM-Based FPGAs

Fault Classification for SRAM-Based FPGAs in the Space Environment for Fault Mitigation

Automated Resource-Aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA Systems

A Novel Hardware/Software Codesign Methodology Based on Dynamic Reconfiguration with Impulse C and Codeveloper

A Reliable Reconfiguration Controller for Fault-Tolerant Embedded Systems on Multi-FPGA Platforms