A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.

Advanced parallel array processor (APAP)

To increase the performance of a pipelined processor executing instructions, conditional instruction execution issues and executes instructions, including but not limited to branches, before the controlling conditions may be available and makes the decision to update the destination as late as possible in the pipeline Conditional instruction execution is further improved by a condition code mask field in instructions to choose those condition code bits to be involved in the decision; by a set condition code flag to enable or disable the setting of a condition code; by stale condition code handling to determine if the logically previous conditionally executing instruction was successful or unsuccessful in setting the condition code and to conditionally execute accordingly; by multiple condition codes so that independent instruction sequences can use condition codes in parallel; and by condition code reservation stations to capture a needed condition code as soon as it becomes available and hold that captured value until needed, thus freeing the condition code as soon as possible for use by other instructions Moving the conditional decision from the point of instruction issue to the point of instruction completion permits branch instructions to be eliminated in many cases; permits conditionally executing instructions directly in line; permits filling the branch umbra following a delayed branch with conditionally executing instructions; and reduces the latency from condition code generation to condition code use

Computer processor with an efficient means of executing many instructions simultaneously

APAP I/O programmable router

A single-instruction-multiple-data (SIMD) array processor is described with a multi-dimensional array of processing elements and control logic for issuing global instructions to the array. Each processing element in the array has individually programmable instruction decoder and a mechanism which enables efficiently programming and reprogramming of the instruction decoder. The present invention teaches a mechanism where the processing elements may be simultaneously updated in response to a global load instruction.

SIMD array processor with global instruction control and reprogrammable instruction decoders

Advanced parallel processor including advanced support hardware

Equipping individual processing elements with an instruction adapter provides an array processor with adaptive spatial-dependent and data-dependent processing capability. The instruction becomes variable, at the processing element level, in response to spatial and data parameters of the data stream. An array processor can be optimized, for example, to carry out very different instructions on spatial-dependent data such as blank margin surrounding the black lines of a sketch. Similarly, the array processor can be optimized for data-dependent values, for example to execute different instructions for positive data values than for negative data values. Providing each processing element with a processor identification register permits an easy setup by flowing the setup values to the individual processing elements, together with setup of condition control values. Each individual adaptive processing element responds to the composite values of original setup and of the data stream to derive the instruction for execution during the cycle. In the usual operation, each adaptive processing element is individually addressed to set up a base instruction; it also is conditionally set up to execute a derived instruction instead of the base instruction. An array processor made up of adaptive processing elements can adapt dynamically to changes in its input data stream, and thus can be dynamically optimized, resulting in greatly enhanced performance at very low incremental cost.

Ching-Chy Wang

Papers

Adaptive instruction processing by array processor having processor identification and data dependent status registers in each processing element