Damascene copper electroplating for on-chip interconnections, a process that we conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition. We discuss here the relationship of additives in the plating bath to superfilling, the phenomenon that results in superconformal coverage, and we present a numerical model which accounts for the experimentally observed profile evolution of the plated metal.

Damascene copper electroplating for chip interconnections

Process gas discharged from a bypass pipe to a gas exhaust system can be prevented from diffusing back to the inside of a process chamber without having to install a dedicated vacuum pump at the downstream side of the bypass pipe. The substrate processing apparatus includes a process chamber accommodating a substrate, a gas supply system supplying process gas from a process gas source to the process chamber for processing the substrate, a gas exhaust system configured to exhaust the process chamber, two or more vacuum pumps installed in series at the gas exhaust system, and a bypass pipe connected between the gas supply system and the gas exhaust system. The most upstream one of the vacuum pumps is a mechanical booster pump, and the bypass pipe is connected between the mechanical booster pump and the rest vacuum pumps located at a downstream side of the mechanical booster pump.

Substrate Processing Apparatus

A fin field-effect transistor (finFET) with improved source/drain regions is provided. In an embodiment, the source/drain regions of the fin are removed while spacers adjacent to the fin remain. An angled implant is used to implant the source/drain regions near a gate electrode, thereby allowing for a more uniform lightly doped drain. The fin may be re-formed by either epitaxial growth or a metallization process. In another embodiment, the spacers adjacent the fin in the source/drain regions are removed and the fin is silicided along the sides and the top of the fin. In yet another embodiment, the fin and the spacers are removed in the source/drain regions. The fins are then re-formed via an epitaxial growth process or a metallization process. Combinations of these embodiments may also be used.

Fin Field-Effect Transistors

Substrate processing systems are described that have a capacitively coupled plasma (CCP) unit positioned inside a process chamber. The CCP unit may include a plasma excitation region formed between a first electrode and a second electrode. The first electrode may include a first plurality of openings to permit a first gas to enter the plasma excitation region, and the second electrode may include a second plurality of openings to permit an activated gas to exit the plasma excitation region. The system may further include a gas inlet for supplying the first gas to the first electrode of the CCP unit, and a pedestal that is operable to support a substrate. The pedestal is positioned below a gas reaction region into which the activated gas travels from the CCP unit.

Semiconductor processing system and methods using capacitively coupled plasma

An exemplary system may include a chamber configured to contain a semiconductor substrate in a processing region of the chamber. The system may include a first remote plasma unit fluidly coupled with a first access of the chamber and configured to deliver a first precursor into the chamber through the first access. The system may still further include a second remote plasma unit fluidly coupled with a second access of the chamber and configured to deliver a second precursor into the chamber through the second access. The first and second access may be fluidly coupled with a mixing region of the chamber that is separate from and fluidly coupled with the processing region of the chamber. The mixing region may be configured to allow the first and second precursors to interact with each other externally from the processing region of the chamber.

Semiconductor processing systems having multiple plasma configurations

Methods and apparatus are provided for forming a metal or metal silicide layer by an electroless deposition technique. In one aspect, a method is provided for processing a substrate including depositing an initiation layer on a substrate surface, cleaning the substrate surface, and depositing a conductive material on the initiation layer by exposing the initiation layer to an electroless solution. The method may further comprise etching the substrate surface with an acidic solution and cleaning the substrate of the acidic solution prior to depositing the initiation layer. The initiation layer may be formed by exposing the substrate surface to a noble metal electroless solution or a borane-containing solution. The conductive material may be deposited with a borane-containing reducing agent. The conductive material may be used as a passivation layer, a barrier layer, a seed layer, or for use in forming a metal silicide layer.

Electroless deposition method

An apparatus and a method of depositing a catalytic layer comprising at least one metal selected from the group consisting of noble metals, semi-noble metals, alloys thereof, and combinations thereof in sub-micron features formed on a substrate. Examples of noble metals include palladium and platinum. Examples of semi-noble metals include cobalt, nickel, and tungsten. The catalytic layer may be deposited by electroless deposition, electroplating, or chemical vapor deposition. In one embodiment, the catalytic layer may be deposited in the feature to act as a barrier layer to a subsequently deposited conductive material. In another embodiment, the catalytic layer may be deposited over a barrier layer. In yet another embodiment, the catalytic layer may be deposited over a seed layer deposited over the barrier layer to act as a “patch” of any discontinuities in the seed layer. Once the catalytic layer has been deposited, a conductive material, such as copper, may be deposited over the catalytic layer. In one embodiment, the conductive material is deposited over the catalytic layer by electroless deposition. In another embodiment, the conductive material is deposited over the catalytic layer by electroless deposition followed by electroplating or followed by chemical vapor deposition. In still another embodiment, the conductive material is deposited over the catalytic layer by electroplating or by chemical vapor deposition.

Electroless deposition method over sub-micron apertures

Electrodeposition of copper–tin alloy thin films for microelectronic applications

Method of depositing a catalytic layer

The present invention provides a composition and method for void-free plating of a metal into high aspect ratio features. The plating process is carried out in a plating solution containing metal at a molar concentration of between about 0.4 M and about 0.9 M, an acid at a concentration of between about 4 mg/L and about 40 mg/L, a suppressor at a concentration of between about 2 mL/L and about 15 mL/L, an accelerator at a concentration of between about 1.5 mL/L and about 8 mL/L, and a leveler at a concentration of between about 4 mL/L and about 11 mL/L.

Chris R. McGuirk

Papers

Electroless deposition method

Electroless deposition method over sub-micron apertures

Electrodeposition of copper–tin alloy thin films for microelectronic applications

Method of depositing a catalytic layer

Process window for gap-fill on very high aspect ratio structures using additives in low acid copper baths