Showing papers by "Christof Paar published in 2000"

A High Performance Reconfigurable Elliptic Curve Processor for GF(2m)

Abstract: This work proposes a processor architecture for elliptic curves cryptosystems over fields GF(2m). This is a scalable architecture in terms of area and speed that exploits the abilities of reconfigurable hardware to deliver optimized circuitry for different elliptic curves and finite fields. The main features of this architecture are the use of an optimized bit-parallel squarer, a digit-serial multiplier, and two programmable processors. Through reconfiguration, the squarer and the multiplier architectures can be optimized for any field order or field polynomial. The multiplier performance can also be scaled according to system's needs. Our results show that implementations of this architecture executing the projective coordinates version of the Montgomery scalar multiplication algorithmcan compute elliptic curve scalar multiplications with arbitrary points in 0.21 msec in the field GF(2167). A result that is at least 19 times faster than documented hardware implementations and at least 37 times faster than documented software implementations.

A high-performance reconfigurable elliptic curve processor for GF(2m)

Abstract: This work proposes a processor architecture for elliptic curves cryptosystems over fields GF(2 m ) This is a scalable architecture in terms of area and speed that exploits the abilities of reconfigurable hardware to deliver optimized circuitry for different elliptic curves and finite fields The main features of this architecture are the use of an optimized bit-parallel squarer, a digit-serial multiplier, and two programmable processors Through reconfiguration, the squarer and the multiplier architectures can be optimized for any field order or field polynomial The multiplier performance can also be scaled according to system's needs Our results show that implementations of this architecture executing the projective coordinates version of the Montgomery scalar multiplication algorithm can compute elliptic curve scalar multiplications with arbitrary points in 021 msec in the field GF(2 167 ) A result that is at least 19 times faster than documented hardware implementations and at least 37 times faster than documented software implementations

An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists.

Abstract: The technical analysis used in determining which of the Advanced Encryption Standard candidates will be selected as the Advanced Encryption Algorithm includes eciency testing of both hardware and software implementations of candidate algorithms. Reprogrammable devices such as Field Programmable Gate Arrays (FPGAs) are highly attractive options for hardware implementations of encryption algorithms as they provide cryptographic algorithm agility, physical security, and potentially much higher performance than software solutions. This contribution investigates the signicance of FPGA implementations of four of the Advanced Encryption Standard candidate algorithm nalists. Multiple architectural implementation options are explored for each algorithm. A strong focus is placed on high throughput implementations, which are required to support security for current and future high bandwidth applications. The implementations of each algorithm will be compared in an eort to determine the most suitable candidate for hardware implementation within commercially available FPGAs.

An FPGA implementation and performance evaluation of the Serpent block cipher

Abstract: With the expiration of the Data Encryption Standard (DES) in 1998, the Advanced Eneryption Standard (AES) development process is well underway. It is hoped that the result of the AES process will be the specification of a new non-classified encryption algorithm that will have the global acceptance achieved by DES as well as the capability of long-term protection of sensitive information. The technical analysis used in determining which of the potential AES candidates will be selected as the Advanced Encryption Algorithm includes efficiency testing of both hardware and software implementations of candidate algorithms. Reprogrammable devices such as Field Programmable Gate Arrays (FPGAs) are highly attractive options for hardware implementations of encryption algorithms as they provide cryptographic algorithm agility, physical security, and potentially much higher performance than software solutions. This contribution investigates the significance of an FPGA implementation of Serpent, one of the Advanced Encryption Standard candidate algorithms. Multiple architecture options of the Serpent algorithm will be explored with a strong focus being placed on a high speed implementation within an FPGA in order to support security for current and future high bandwidth applications. One of the main findings is that Serpent can be implemented with encryption rates beyond 4 Gbit/s on current FPGAs.

Cryptographic hardware and embedded systems - CHES 2000 : second international workshop, Worcester, MA, USA, August 17-18, 2000 : proceedings

Abstract: Invited Talk.- Software Implementation of Elliptic Curve Cryptography over Binary Fields.- Implementation of Elliptic Curve Cryptosystems.- Implementation of Elliptic Curve Cryptographic Coprocessor over GF(2m) on an FPGA.- A High-Performance Reconfigurable Elliptic Curve Processor for GF(2m).- Fast Implementation of Elliptic Curve Defined over GF(pm) on CalmRISC with MAC2424 Coprocessor.- Power and Timing Analysis Attacks.- Protecting Smart Cards from Passive Power Analysis with Detached Power Supplies.- Smartly Analyzing the Simplicity and the Power of Simple Power Analysis on Smartcards.- Power Analysis Attacks and Algorithmic Approaches to their Countermeasures for Koblitz Curve Cryptosystems.- A Timing Attack against RSA with the Chinese Remainder Theorem.- Hardware Implementation of Block Ciphers.- A Comparative Study of Performance of AES Final Candidates Using FPGAs.- A Dynamic FPGA Implementation of the Serpent Block Cipher.- A 12 Gbps DES Encryptor/Decryptor Core in an FPGA.- A 155 Mbps Triple-DES Network Encryptor.- Hardware Architectures.- An Energy Efficient Reconfigurable Public-Key Cryptography Processor Architecture.- High-Speed RSA Hardware Based on Barret's Modular Reduction Method.- Data Integrity in Hardware for Modular Arithmetic.- A Design for Modular Exponentiation Coprocessor in Mobile Telecommunication Terminals.- Invited Talk.- How to Explain Side-Channel Leakage to Your Kids.- Power Analysis Attacks.- On Boolean and Arithmetic Masking against Differential Power Analysis.- Using Second-Order Power Analysis to Attack DPA Resistant Software.- Differential Power Analysis in the Presence of Hardware Countermeasures.- Arithmetic Architectures.- Montgomery Multiplier and Squarer in GF(2m).- A Scalable and Unified Multiplier Architecture for Finite Fields GF(p) and GF(2m).- Montgomery Exponentiation with no Final Subtractions: Improved Results.- Physical Security and Cryptanalysis.- Physical Security Devices for Computer Subsystems: A Survey of Attacks and Defenses.- Software-Hardware Trade-Offs: Application to A5/1 Cryptanalysis.- New Schemes and Algorithms.- MiniPASS: Authentication and Digital Signatures in a Constrained Environment.- Efficient Generation of Prime Numbers.

Public-Key Cryptography with Arbitrary Finite Fields

Abstract: This contribution proposes text for possible inclusion in IEEE P1363a specifying support for additional finite fields in the DL and EC settings. In particular, this contribution generalizes IEEE P1363 to support all finite fields. Like IEEE P1363a, it is written as updates to the IEEE P1363 document. It is intended for discussion and review at the March 16-17, 2000, IEEE P1363 working group meeting. The contribution has not yet been approved by the working group.