C
Christopher Batten
Researcher at Cornell University
Publications - 64
Citations - 2404
Christopher Batten is an academic researcher from Cornell University. The author has contributed to research in topics: Computer science & Python (programming language). The author has an hindex of 20, co-authored 57 publications receiving 2177 citations. Previous affiliations of Christopher Batten include Massachusetts Institute of Technology.
Papers
More filters
Proceedings ArticleDOI
Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics
Christopher Batten,Ajay Joshi,Jason S. Orcutt,Anatol Khilo,B. Moss,C.W. Holzwarth,Milos A. Popovic,Hanqing Li,Henry I. Smith,Judy L. Hoyt,Franz X. Kärtner,Rajeev J. Ram,Vladimir Stojanovic,Krste Asanovic +13 more
TL;DR: A new monolithic silicon photonics technology suited for integration with standard bulk CMOS processes, which reduces costs and improves opto-electrical coupling compared to previous approaches is presented, which supports dense wavelength-division multiplexing with dozens of wavelengths per waveguide.
Proceedings ArticleDOI
Silicon-photonic clos networks for global on-chip communication
Ajay Joshi,Christopher Batten,Yong-Jin Kwon,Scott Beamer,Imran Shamim,Krste Asanovic,Vladimir Stojanovic +6 more
TL;DR: In this paper, the authors explore using photonics to implement low-diameter non-blocking crossbar and Clos networks, and show that a 64-tile photonic Clos network consumes significantly less optical power, thermal tuning power, and area compared to global photonic crossbars over a range of photonic device parameters.
Journal ArticleDOI
Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics
Christopher Batten,Ajay Joshi,Jason S. Orcutt,Anatol Khilo,B. Moss,C.W. Holzwarth,Milos A. Popovic,Hanqing Li,Henry I. Smith,Judy L. Hoyt,Franz X. Kärtner,Rajeev J. Ram,Vladimir Stojanovic,Krste Asanovic +13 more
TL;DR: A new monolithic silicon-photonic technology is introduced, which uses a standard bulk CMOS process to reduce costs and improve energy efficiency, and the logical and physical implications of leveraging this technology in processor-to-memory networks are explored.
Journal ArticleDOI
The Vector-Thread Architecture
Ronny Krashinsky,Christopher Batten,Mark Hampton,Steve Gerding,Brian Pharris,Jared Casper,Krste Asanovic +6 more
TL;DR: SCALE, an instantiation of the vector-thread (VT) architecture designed for low-power and high-performance embedded systems, is presented and it is shown that its performance is competitive with larger and more complexprocessors.
Journal ArticleDOI
The vector-thread architecture
B. Krashinsky,Christopher Batten,Mark Hampton,Steve Gerding,B. Pharris,Jared Casper,Krste Asanovic +6 more
TL;DR: SCALE, an instantiation of the VT architecture designed for low-power and high-performance embedded systems, is presented and its performance is competitive with larger and more complex processors.