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Ajay Joshi
Researcher at Boston University
Publications - 124
Citations - 2699
Ajay Joshi is an academic researcher from Boston University. The author has contributed to research in topics: Network on a chip & Network topology. The author has an hindex of 22, co-authored 112 publications receiving 2306 citations. Previous affiliations of Ajay Joshi include University of Missouri & University of the West Indies.
Papers
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Proceedings ArticleDOI
Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics
Christopher Batten,Ajay Joshi,Jason S. Orcutt,Anatol Khilo,B. Moss,C.W. Holzwarth,Milos A. Popovic,Hanqing Li,Henry I. Smith,Judy L. Hoyt,Franz X. Kärtner,Rajeev J. Ram,Vladimir Stojanovic,Krste Asanovic +13 more
TL;DR: A new monolithic silicon photonics technology suited for integration with standard bulk CMOS processes, which reduces costs and improves opto-electrical coupling compared to previous approaches is presented, which supports dense wavelength-division multiplexing with dozens of wavelengths per waveguide.
Proceedings ArticleDOI
Silicon-photonic clos networks for global on-chip communication
Ajay Joshi,Christopher Batten,Yong-Jin Kwon,Scott Beamer,Imran Shamim,Krste Asanovic,Vladimir Stojanovic +6 more
TL;DR: In this paper, the authors explore using photonics to implement low-diameter non-blocking crossbar and Clos networks, and show that a 64-tile photonic Clos network consumes significantly less optical power, thermal tuning power, and area compared to global photonic crossbars over a range of photonic device parameters.
Journal ArticleDOI
Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics
Christopher Batten,Ajay Joshi,Jason S. Orcutt,Anatol Khilo,B. Moss,C.W. Holzwarth,Milos A. Popovic,Hanqing Li,Henry I. Smith,Judy L. Hoyt,Franz X. Kärtner,Rajeev J. Ram,Vladimir Stojanovic,Krste Asanovic +13 more
TL;DR: A new monolithic silicon-photonic technology is introduced, which uses a standard bulk CMOS process to reduce costs and improve energy efficiency, and the logical and physical implications of leveraging this technology in processor-to-memory networks are explored.
Proceedings ArticleDOI
Measuring Program Similarity: Experiments with SPEC CPU Benchmark Suites
TL;DR: This paper applies their methodology to the SPEC CPU2000 benchmark suite and demonstrates that a subset of 8 programs can be used to effectively represent the entire suite, and proves the usefulness of this subset by using it to estimate the average IPC and L1 data cache miss-rate of the entire suites.
Journal ArticleDOI
Measuring benchmark similarity using inherent program characteristics
TL;DR: From the study of the similarity between the four generations of SPEC CPU benchmark suites, it is found that, other than a dramatic increase in the dynamic instruction count and increasingly poor temporal data locality, the inherent program characteristics have more or less remained unchanged.