Computer and Robot Vision Vol. 1, by R.M. Haralick and Linda G. Shapiro, Addison-Wesley, 1992, ISBN 0-201-10887-1.

Computer and Robot Vision

A modular intelligent transportation system, comprising an environmentally protected enclosure, a system communications bus, a processor module, communicating with said bus, having a image data input and an audio input, the processor module analyzing the image data and/or audio input for data patterns represented therein, having at least one available option slot, a power supply, and a communication link for external communications, in which at least one available option slot can be occupied by a wireless local area network access point, having a communications path between said communications link and said wireless access point, or other modular components.

Modular intelligent transportation system

Automated detection of vehicles in front is an integral component of many advanced driver-assistance systems (ADAS), such as collision mitigation, automatic cruise control (ACC), and automatic headlamp dimming. We present a novel image processing system to detect and track vehicle rear-lamp pairs in forward-facing color video. A standard low-cost camera with a complementary metal-oxide semiconductor (CMOS) sensor and Bayer red-green-blue (RGB) color filter is used and could be utilized for full-color image display or other color image processing applications. The appearance of rear lamps in video and imagery can dramatically change, depending on camera hardware; therefore, we suggest a camera-configuration process that optimizes the appearance of rear lamps for segmentation. Rear-facing lamps are segmented from low-exposure forward-facing color video using a red-color threshold. Unlike previous work in the area, which uses subjective color threshold boundaries, our color threshold is directly derived from automotive regulations and adapted for real-world conditions in the hue-saturation-value (HSV) color space. Lamps are paired using color cross-correlation symmetry analysis and tracked using Kalman filtering. A tracking-based detection stage is introduced to improve robustness and to deal with distortions caused by other light sources and perspective distortion, which are common in automotive environments. Results that demonstrate the system's high detection rates, operating distance, and robustness to different lighting conditions and road environments are presented.

Rear-Lamp Vehicle Detection and Tracking in Low-Exposure Color Video for Night Conditions

This paper analyses different hardware sorting architectures in order to implement a highly scaleable sorter for solving huge problems at high performance up to the GB range in linear time complexity. It will be proven that a combination of a FIFO-based merge sorter and a tree-based merge sorter results in the best performance at low cost. Moreover, we will demonstrate how partial run-time reconfiguration can be used for saving almost half the FPGA resources or alternatively for improving the speed. Experiments show a sustainable sorting throughput of 2GB/s for problems fitting into the on-chip FPGA memory and 1 GB/s when using external memory. These values surpass the best published results on large problem sorting implementations on FPGAs, GPUs, and the Cell processor.

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FPGASort: a high performance sorting architecture exploiting run-time reconfiguration on fpgas for large problem sorting

Run-time Partial Reconfiguration (PR) speed is significant in applications especially when fast IP core switching is required. In this paper, we propose to use Direct Memory Access (DMA), Master (MST) burst, and a dedicated Block RAM (BRAM) cache respectively to reduce the reconfiguration time. Based on the Xilinx PR technology and the Internal Configuration Access Port (ICAP) primitive in the FPGA fabric, we discuss multiple design architectures and thoroughly investigate their performance with measurements for different partial bitstream sizes. Compared to the reference OPB HWICAP and XPS HWICAP designs, experimental results showthatDMA HWICAP and MST HWICAP reduce the reconfiguration time by one order of magnitude, with little resource consumption overhead. The BRAM HWICAP design can even approach the reconfiguration speed limit of the ICAP primitive at the cost of large Block RAM utilization.

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Run-time Partial Reconfiguration speed investigation and architectural design space exploration

Dynamic and partial reconfiguration (DPR) is a special feature offered by Xilinx Field Programmable Gate Arrays (FPGAs), giving the designer the ability to reconfigure a certain portion of the FPGA during run-time without influencing the other parts. This feature allows the hardware to be adaptable to any potential situation. For some applications, such as video-based driver assistance, the time needed to exchange a certain portion of the device might be critical. This paper addresses problems, limitations and results of on-chip reconfiguration that enable the user to decide whether DPR is suitable for a certain design prior to its implementation. A method is therefore introduced to calculate the expected reconfiguration throughput and latency. In addition, an IP core is presented that enables fast on-chip DPR close to the maximum achievable speed. Compared to an alternative state-of-the art realization, an increase in speed by a factor of 58 can be obtained.

A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput

The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconfiguration, also known as dynamic partial reconfiguration (DPR). Taking this concept one step further, partial dynamic self-reconfiguration becomes possible through the internal configuration access port (ICAP). In this paper a framework for lowering reconfiguration times using the combitgen tool to reduce the overhead found within bitstreams, along with a completely new, very simple and area efficient ICAP controller that is connected directly to the processor local bus (PLB) and is equipped with direct memory access (DMA) capabilities is presented. Using this PLB Master ICAP controller, it is possible to reach the maximum practical throughput that can be achieved with the ICAP interface of Virtex-II Pro devices. Compared to an alternative realization using the OPBHWICAP provided by Xilinx (a slave attachment on the on-chip peripheral bus), it is possible to achieve improvements concerning reconfiguration times by a factor of 20.

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A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration

In this paper we show a reconfigurable hardware architecture for the acceleration of video-based driver assistance applications in future automotive systems. The concept is based on a separation of pixel-level operations and high level application code. Pixel-level operations are accelerated by coprocessors, whereas high level application code is implemented fully programmable on standard PowerPC CPU cores to allow flexibility for new algorithms. In addition, the application code is able to dynamically reconfigure the coprocessors available on the system, allowing for a much larger set of hardware accelerated functionality than would normally fit onto a device. This process makes use of the partial dynamic reconfiguration capabilities of Xilinx Virtex FPGAs.

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Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system

Using dynamically reconfigurable hardware is useful especially when a high degree of flexibility is demanded and the application requires inherent parallelism to achieve real-time constraints. Depending on various driving conditions different algorithms have to be used for video processing. These different algorithms require different hardware accelerator engines, which are loaded into the AutoVision chip at run-time of the system. The novelties presented in this paper are the determination of the maximum frequency for dynamic partial reconfiguration of Xilinx Virtex-II Pro, Virtex-4 and Virtex-5 devices and a modified overclocked version of the ICAP controller. In addition an online verification approach is presented that can determine configuration errors that might be caused by configuring a device above the specified frequencies. This results in a reconfiguration throughput which is three times higher than the maximum throughput specified by Xilinx.

Christopher Claus

Papers

A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput

A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration

Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system

Towards rapid dynamic partial reconfiguration in video-based driver assistance systems

Autovision-A Run-time Reconfigurable MPSoC Architecture for future Driver Assistance Systems