C
Christopher John Nicol
Researcher at Alcatel-Lucent
Publications - 17
Citations - 468
Christopher John Nicol is an academic researcher from Alcatel-Lucent. The author has contributed to research in topics: Digital signal processor & Multiplier (economics). The author has an hindex of 9, co-authored 17 publications receiving 468 citations. Previous affiliations of Christopher John Nicol include Agere Systems.
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Patent
Power reduction in a multiprocessor digital signal processor based on processor load
TL;DR: In this article, a controller in a multi-processor chip allocates tasks to the individual processors to equalize processing load among the chips, then the controller lowers the clock frequency on the chip to as low a level as possible while assuring proper operation, and finally reduces the supply voltage.
Journal ArticleDOI
A unified turbo/Viterbi channel decoder for 3GPP mobile wireless in 0.18-/spl mu/m CMOS
M. Bickerstaff,David Garrett,T. Prokop,C. Thomas,Benjamin John Widdup,Gongyu Zhou,Christopher John Nicol,Ran-Hong Yan +7 more
TL;DR: A 3GPP-compliant 4.1 Mb/s channel decoder supports data and voice calls in a unified Turbo/Viterbi architecture with hardware interleaver memory and pattern computation.
Patent
Power reduction in a multiprocessor digital signal processor
TL;DR: In this article, a controller in a multi-processor chip allocates tasks to individual processors to equalize processing load among the chips, then the controller lowers the clock frequency on the chip to as low a level as possible while assuring proper operation, and finally reduces the supply voltage.
Patent
Apparatus and method for adaptive reduction of power consumption in integrated circuits
TL;DR: In this paper, power consumption in program implemented circuits and the like is dynamically controlled in accordance with the circuit performance over time, not by reducing switched capacitance as was done in prior hardware circuit implementations, but by dynamically reducing the number of machine cycles required to implement the desired circuit at an acceptable performance level.
Patent
Method and memory cache for cache locking on bank-by-bank basis
TL;DR: Bank-by-bank locking as mentioned in this paper is a technique to prevent critical code from being flushed out of the cache, where a register is maintained to rank the banks from the most recently used to the least used.