A catheter anchoring system is provided to securely anchor to a patient's skin a catheter and fluid supply tube interconnection. The anchoring system comprises a retainer configured to receive a catheter adaptor in a variety of positions. The adaptor interconnects the catheter and the fluid supply tube. In one embodiment the adaptor has a radial recess that circumscribes the adaptor. The anchoring system additionally includes a flexible, adhesive anchor pad which can supports a tube clip, as well as the retainer. The retainer includes a channel that is configured to receive the adaptor in a snap-fit manner. The retainer also includes a plurality of laterally arranged projections that extend from a channel wall and into a channel. Each radial recess is sized to receive and to capture at least a portion of the projection of the retainer so as to inhibit the adaptor from moving within the channel.

Catheter anchoring system

A 20-bit incremental ADC for battery-powered sensor applications is presented. It is based on an energy-efficient zoom ADC architecture, which employs a coarse 6-bit SAR conversion followed by a fine 15-bit ΔΣ conversion. To further improve its energy efficiency, the ADC employs integrators based on cascoded dynamic inverters for extra gain and PVT tolerance. Dynamic error correction techniques such as auto-zeroing, chopping and dynamic element matching are used to achieve both low offset and high linearity. Measurements show that the ADC achieves 20-bit resolution, 6 ppm INL and 1 μV offset in a conversion time of 40 ms, while drawing only 3.5 μA current from a 1.8 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 182.7 dB. The 0.35 mm2 chip was fabricated in a standard 0.16 μm CMOS process.

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A 6.3 µW 20 bit Incremental Zoom-ADC with 6 ppm INL and 1 µV Offset

The successive-approximation-register (SAR) architecture is well known for its high power efficiency in medium-resolution analog-to-digital converters (ADCs). However, when considered for high-precision applications, SAR ADCs suffer from non-linearity resulting from capacitor mismatch and limited dynamic range due to comparator noise. This work presents a mismatch error shaping (MES) technique for oversampling SAR ADCs to achieve 105 dB in-band SFDR without calibration. The capacitor mismatch error is first-order high-pass filtered by simply delaying the reset of LSB capacitor array after sampling. The comparator thermal and flicker noise are also first-order shaped to high frequencies by noise shaping. The prototype in 55 nm CMOS occupies 0.072 mm2 and achieves a peak SNDR of 101 dB over 1 kHz bandwidth. It consumes 15.7 $\mu \text {W}$ from a 1.2 V supply at 1 MS/s and can be configured to Nyquist mode up to 5 MS/s. These features enable the application of SAR ADCs in high-precision, multi-purpose sensor readout interfaces.

An Oversampling SAR ADC With DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS

At the turn of this century, there was widespread concern that the performance of analog-to-digital converters (ADCs) might have reached a saturation point and would, in fact, deteriorate as we began to scale into deep submicron CMOS technology. The past 15 years of innovation have clearly refuted such fears. Driven by a combination of application pull, architectural modifications, and relentless optimization, we have seen steady improvements in several key performance metrics.

The Race for the Extra Decibel: A Brief Review of Current ADC Performance Trajectories

A 14-bit SAR ADC is presented that achieves 73.6 dB SNDR at 80 MSPS while using a 1.2-V-only supply. In order to overcome throughput limitations common to conventional SAR ADCs, several techniques are proposed. First, a flash sub-ADC is utilized to resolve the 5 MSBs quickly prior to SAR sequential decisions of the LSBs. Second, the DAC operation is time-interleaved by a factor of 2, increasing speed while allowing a single comparator to be shared between all DACs. Third, fully on-chip DAC charge redistribution allows the DAC settling time to be improved by more than an order of magnitude compared to conventional techniques. Finally, the ADC is fully self-timed through the use of a replica timer circuit in order to take full advantage of the fast DAC settling and comparator decisions. Despite the increased speed, the ADC consumes only 31.1 mW and occupies a core area of 0.55 mm2.

A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS

This paper presents a precision 18-bit 12.5 MS/s ADC that was designed primarily for digital X-ray imaging systems. This ADC was intended to have a faster output data rate than the precision successive approximation ADCs normally chosen for these systems but with similar DC accuracy and dynamic range. The chosen architecture consists of a pipeline of two multi-bit successive approximation converters. The first successive approximation ADC generates an initial coarse conversion result. The DACs within this converter are then used to generate a residue which is amplified by a residue amplifier before being converted by a second successive approximation ADC. Four comparators within each ADC allow 2 bits to be determined each bit trial. Capacitor mismatch errors are digitally corrected with error coefficients stored in non-volatile memory. Dither is used to reduce the effect of errors in the flash ADC within the second ADC. The ADC was implemented on 0.25 m CMOS process with PIP capacitors and achieves a SNR of 93 dB with a 50 kHz input tone. INL and DNL are within LSB and LSB respectively. Power consumption is 105 mW, excluding LVDS interface power.

An 18 b 12.5 MS/s ADC With 93 dB SNR

An analog to digital converter is provided in which the outputs of first and second digital to analog converters DACl and DAC2 are combined in a combining circuit so as to form a plurality of decision thresholds. This enables two or more bits to be determined in a single trial.

Analog-to-digital converter

An ADC ( 1 ) of balanced architecture for determining a digital word corresponding to a sampled voltage of an input signal from an input line ( 33 ) comprises a first capacitor circuit ( 2 ) comprising a most significant capacitor array ( 4 ) and a least significant capacitor array ( 5 ) which are capacitively coupled by a coupling capacitor C c1 . A second capacitor circuit ( 29 ) coupled to ground balances the first capacitor circuit ( 2 ). A differential comparator 27 compares the voltage on the first capacitor circuit ( 2 ) with that on the second capacitor circuit ( 29 ). A SAR ( 42 ) responsive to the output of the differential comparator ( 27 ) outputs switch bits to a main switch network ( 32 ) for selectively switching the capacitors of the first capacitor circuit ( 2 ) to respective high and low voltage reference lines ( 34 ) and ( 35 ) until the voltage on first and second inputs ( 26 ) and ( 28 ) of the differential comparator ( 27 ) are equal for determining the digital word corresponding to the sampled voltage on the input line ( 33 ). A first calibration circuit ( 49 ) for calibrating the coupling capacitor (C c1 ) for compensating for under or over capacitance of the coupling capacitor C c1 comprises a plurality of binary weighted first calibrating capacitors ( 51 ) to ( 56 ) which are coupled by a calibration coupling capacitor C 4 to the least significant capacitor array ( 5 ). A first calibration switch network ( 57 ) is provided for selectively coupling the first calibrating capacitors ( 51 ) to ( 56 ) to either the second input ( 28 ) of the differential comparator ( 27 ), the first input ( 26 ) of the differential comparator ( 27 ), or ground. By coupling appropriate ones of the first calibrating capacitors ( 51 ) to ( 56 ) to the second input ( 28 ) of the differential comparator ( 27 ) over capacitance of the coupling capacitor (C c1 ) is compensated for, and under capacitance is compensated for by coupling appropriate ones of the first calibrating capacitors ( 51 ) to ( 56 ) to the first input ( 26 ) of the differential comparator ( 27 ).

Analog to digital converter with a calibration circuit for compensating for coupling capacitor errors, and a method for calibrating the analog to digital converter

A SAR converter having enhanced performance by virtue of effectively pre-loading the SAR's most significant bits with a value that makes the associated DAC output almost equal to the signal to be converted. A normal SAR conversion is then completed with the SAR bits that have not been pre-loaded. The value used to pre-load the most significant bits of the SAR is preferably obtained from a low-resolution, high-speed converter, such as a flash. The range of DAC bits used in the normal SAR part of the conversion may be increased such that errors up to a certain magnitude in the high-speed converter can be corrected. A method for performing an enhanced SAR conversion is also described.

Successive approximation analog-to-digital converter with pre-loaded SAR registers

This paper presents an 18 bit 5 MS/s SAR ADC. It has a dynamic range of 100.2 dB, SNR of 99 dB, INL of ±2 ppm and DNL of ±0.4 ppm. It has currently the lowest noise floor of any monolithic Nyquist converter relative to the full scale input (21.9 nV/√Hz, ±5V full scale) known to the author, all of this is achieved with an ADC core power of 30.52 mW giving a Schreier figure of merit of 179.3 dB [1]. Architectural choices such as the use of a residue amplifier are outlined that enable the high sample rate, low noise and power efficiency. The design is implemented on 0.18 μm CMOS with MIM capacitors and both 1.8 V and 5 V MOS devices. An LVDS interface is used to transfer the ADC result off chip.

Christopher Peter Hurrell

Papers

An 18 b 12.5 MS/s ADC With 93 dB SNR

Analog-to-digital converter

Analog to digital converter with a calibration circuit for compensating for coupling capacitor errors, and a method for calibrating the analog to digital converter

Successive approximation analog-to-digital converter with pre-loaded SAR registers

An 18 b 5 MS/s SAR ADC with 100.2 dB dynamic range