A new gravity-measuring device uses ultracold atoms generated by a centimeter-wide atom chip, which might lead to a shoebox-sized gadget.

Atom-Chip Fountain Gravimeter

Here we review the field of atom chips in the context of Bose–Einstein Condensates (BEC) as well as cold matter in general. Twenty years after the first realization of the BEC and 15 years after the realization of the atom chip, the latter has been found to enable extraordinary feats: from producing BECs at a rate of several per second, through the realization of matter-wave interferometry, and all the way to novel probing of surfaces and new forces. In addition, technological applications are also being intensively pursued. This review will describe these developments and more, including new ideas which have not yet been realized.

https://tandfonline.com/doi/pdf/10.1080/09500340.2016.1178820

Fifteen years of cold matter on the atom chip: promise, realizations, and prospects.

Here we review the field of atom chips in the context of Bose-Einstein Condensates (BEC) as well as cold matter in general. Twenty years after the first realization of the BEC and fifteen years after the realization of the atom chip, the latter has been found to enable extraordinary feats: from producing BECs at a rate of several per second, through the realization of matter-wave interferometry, and all the way to novel probing of surfaces and new forces. In addition, technological applications are also being intensively pursued. This review will describe these developments and more, including new ideas which have not yet been realized.

Fifteen Years of Cold Matter on the Atom Chip: Promise, Realizations, and Prospects

This paper describes the development, fabrication and examination of an atom chip through silicon vias (TSV), which is anodically bonded with a Pyrex glass cell to form an ultra-high-vacuum system for the application of Bose–Einstein condensation (BEC) experiments. The silicon via is etched by the inductively coupled plasma reactive ion etch and filled by copper plating technology. The metal wires on both sides of the atom chips are patterned by the lithography process. Three different sizes of TSV are made and tested by continuously applying a maximum current of 17 A under the vacuum (70 Torr) and in air. In addition, after the thermal cycling of an anodic bonding process (requested at 350 °C) and a high electric field of 1000 V m−1, the TSV on atom chips can still hold the ultra-high vacuum (UHV). The conductive and vacuum yields of the TSV improved from 50% to 100% and from 75% to 81.25%, respectively after the modification of the fabrication process. Finally, the UHV test of TSV on atom chips at room temperature can be reached at 8 × 10−10 Torr, thus satisfying the requirements of atomic physics experiments under the UHV environment.

https://iopscience.iop.org/article/10.1088/0960-1317/23/8/085004/pdf

The development of an atom chip with through silicon vias for an ultra-high-vacuum cell

This study presents a double-layer atom chip that provides users with increased diversity in the design of the wire patterns and flexibility in the design of the magnetic field. It is more convenient for use in atomic physics experiments. A negative photoresist, SU-8, was used as the insulating layer between the upper and bottom copper wires. The electrical measurement results show that the upper and bottom wires with a width of 100 µm can sustain a 6 A current without burnout. Another focus of this study is the double-layer atom chips integrated with the through silicon via (TSV) technique, and anodically bonded to a Pyrex glass cell, which makes it a desired vacuum chamber for atomic physics experiments. Thus, the bonded glass cell not only significantly reduces the overall size of the ultra-high-vacuum (UHV) chamber but also conducts the high current from the backside to the front side of the atom chip via the TSV under UHV (9.5 × 10−10 Torr). The TSVs with a diameter of 70 µm were etched through by the inductively coupled plasma ion etching and filled by the bottom-up copper electroplating method. During the anodic bonding process, the electroplated copper wires and TSVs on atom chips also need to pass the examination of the required bonding temperature of 250 °C, under an applied voltage of 1000 V. Finally, the UHV test of the double-layer atom chips with TSVs at room temperature can be reached at 9.5 × 10−10 Torr, thus satisfying the requirements of atomic physics experiments under an UHV environment.

https://iopscience.iop.org/article/10.1088/0960-1317/24/4/045013/pdf

The fabrication of a double-layer atom chip with through silicon vias for an ultra-high-vacuum cell

This paper describes the design and fabrication of planarized multilayer atom chips for an ultrahigh-vacuum system in atomic physics experiments. A fabrication process is developed to define micrometer-scale wire patterns on a silicon substrate and wires are plated by copper electroplating. SU-8 is chosen as the isolation layer between the upper and bottom wires, and its thickness, surface flatness and surface roughness (Ra = 5 nm) are controlled by the chemical–mechanical planarization process. A reflectivity of nearly 90% is measured on the chip surface; thus, the former method of attaching a silver mirror is unnecessary (Du et al 2004 Phys. Rev. A 70 053606). A heat dissipation copper block is incorporated in our chip design to increase the sustainable current densities of upper wires of more than 3.8 × 105 A cm−2. Results show the improvement of 55.74%, compared with the nonheat dissipation design (2.44 × 105 A cm−2), and thus meeting the requirements for chip-based atom trapping experiments.

http://iopscience.iop.org/article/10.1088/0960-1317/21/12/125009/pdf

Chung-Wen Weng

Papers

Design, microfabrication and characterization of planarized multilayer atom chips with enhanced heat dissipation