The logic simulator MOSSIM is designed specifically to serve the needs of the MOS LSI designer. It models a MOS circuit as a network of field-effect transistor "switches", with node states 0, 1, and X (unknown) and transistor states "open", "closed", and "unknown". MOSSIM has proved quite versatile and accurate in simulating a variety of MOS designs including ones for which the network was extracted automatically from the mask specifications. Because it models the network at a logical level, it has a performance comparable to conventional logic gate simulators.

MOSSIM: A Switch-Level Simulator for MOS LSI

This paper describes the design, implementation and performance of a fiat edge-based circuit extractor for NMOS circuits. The extractor is able to work on large and complex designs, it can handle arbitrary geometry, and outputs a comprehensive wirelist. Measurements show that the run time of the edge-based algorithm used is linear in size of the circuit, with low implementation overheads. The extractor is capable of analyzing a circuit with 20,000 transistors in less than 30 minutes of CPU time on a VAX 11/780. The high performance of the extractor has changed the role that a circuit extractor played in the design process, as it is now possible to extract a chip a number of times during the same session.

ACE: A Circuit Extractor

We present algorithms for performing connectivity analysis, transistor identification, and boolean geometric operations with region numbering. Previous methods all require O(n) space where n is the number of edges in the circuit artwork; our method takes only O(√n) space and can therefore handle circuits of any foreseeable size. Our algorithms are based on traditional scanline techniques in such a way that any implementation of our method will be at least as fast, as well as more compact. Statistics on one such implementation are presented.

Space Efficient Algorithms for VLSI Artwork Analysis

ALI is a procedural language to specify VLSI layouts. It allows the designer to describe layouts without reference to the sizes and positions of the layout elements or to the distances between them. Among the interesting characteristics of ALI are that it does not need design rule checking, is easy to extend, facilitates the division of labor and permits the easy update of a layout to new design rules or to new processes. The general features of the language and the experience gained with a preliminary implementation of it are described.

ALI: A Procedural Language to Describe VLSI Layouts

a a a 1-Abstract This thesis presents a new CAD simulation method for determining waveform estimates of MOS circuits. The methods are particularly useful in determining the delay times and coupling noise voltages of interconnection networks. Additionally, switching devices are also accurately emulated with a macromodeled equivalent circuit. The moment representation, based on the Laplace Transform, is used as the model for both signals and transfer functions of interconnection networks. A large interconnection network can be modeled by a small number of polynomial terms, making network analysis much simpler, computationally. A new matrix algorithm is developed for solving for the moment representation of almost any linear network. Transistor switching circuits are modeled by macromodeled linear network equivalents. On CMOS test circuits, after several logic stages the moment representation waveforms deviated no more than 10% from SPICE's waveforms, but were computed substantially faster than SPICE. The simulation speed is further improved by "compiling" results, in which an entire switching and interconnection circuit is represented by a macromodeled moment representation approximation. Thesis Supervisor: Jonathan Allen Professor 3 4 IF __ _ _ __ dir 00 Acknowledgments First, I would like to thank Jonathan Allen, my advisor, for his inspiration and encouragement , and for providing the flexibility to define my own work as it progressed. Thanks also to my thesis readers, John Wyatt and Jacob White, for actually reading all 182 pages and for providing good feedback. I thank my friends-particularly Keith Nabors, Andy Ayers and Don Baltus, who expressed occasional interest in this work, and Bob Armstrong, Cyrus Bamji, Barry Thompson and Mark Reichelt, who have been around on the eighth floor through the whole thing. I also thank Dorothy Fleischer. Mostly, I thank my wife, Lynne, for three things: her technical assistance in the form of the work frequently cited in Chapter 6, her emotional support, and her patience as I strived to make this thesis as good as possible. Lastly, I gratefully acknowledge my sponsor, the Joint Services Electronics Program, for supporting this research.

Modeling and simulation of VLSI interconnections with moments

: Current methods of designing Very Large Scale Integrated (VLSI) chips do not insure that the chips will perform correctly when manufactured. Because the turnaround time on chip fabrication varies from a few weeks to a few months, a scheme other than try it and see if it works is needed. Checking of chips by hand simulation and visual inspection of checkplots will not catch all of the errors. In addition, the number of transistors per chip is likely to increase from ten thousand to over a million in the next few years. This increase in complexity precludes any manual verification methods; some better method is needed. A series of programs that use the actual mask descriptions for input are described. These programs perform various levels of checks on the masks, yielding files suitable for simulation. Some of the checks are the usual 'design rule' checks of looking for minimum line widths and adequate spacing between wires. However, there are many more constraints in VLSI circuits than are expressed by usual design rules. The programs check these constraints using the mask descriptions as input. All of the errors mentioned so far can be classified as syntactic errors; in addition, certain errors are detected. The detection of semantic errors requires various levels of simulation. The input to the simulators is derived from the artwork.

https://apps.dtic.mil/sti/pdfs/ADA087040.pdf

Clark Marshall Baker

Papers

Artwork Analysis Tools for VLSI Circuits.