Open Access
Artwork Analysis Tools for VLSI Circuits.
Clark Marshall Baker
- pp 11
TLDR
Current methods of designing Very Large Scale Integrated (VLSI) chips do not insure that the chips will perform correctly when manufactured, so some better method is needed to catch all of the errors.Abstract:
: Current methods of designing Very Large Scale Integrated (VLSI) chips do not insure that the chips will perform correctly when manufactured. Because the turnaround time on chip fabrication varies from a few weeks to a few months, a scheme other than try it and see if it works is needed. Checking of chips by hand simulation and visual inspection of checkplots will not catch all of the errors. In addition, the number of transistors per chip is likely to increase from ten thousand to over a million in the next few years. This increase in complexity precludes any manual verification methods; some better method is needed. A series of programs that use the actual mask descriptions for input are described. These programs perform various levels of checks on the masks, yielding files suitable for simulation. Some of the checks are the usual 'design rule' checks of looking for minimum line widths and adequate spacing between wires. However, there are many more constraints in VLSI circuits than are expressed by usual design rules. The programs check these constraints using the mask descriptions as input. All of the errors mentioned so far can be classified as syntactic errors; in addition, certain errors are detected. The detection of semantic errors requires various levels of simulation. The input to the simulators is derived from the artwork.read more
Citations
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Proceedings ArticleDOI
MOSSIM: A Switch-Level Simulator for MOS LSI
TL;DR: The logic simulator MOSSIM has proved quite versatile and accurate in simulating a variety of MOS designs including ones for which the network was extracted automatically from the mask specifications.
Proceedings ArticleDOI
ACE: A Circuit Extractor
TL;DR: The design, implementation and performance of a flat edge-based circuit extractor for NMOS circuits is described, which is capable of analyzing a circuit with 20,000 transistors in less than 30 minutes of CPU time on a VAX 11/780.
Proceedings ArticleDOI
Space Efficient Algorithms for VLSI Artwork Analysis
TL;DR: Algorithms for performing connectivity analysis, transistor identification, and boolean geometric operations with region numbering are presented based on traditional scanline techniques in such a way that any implementation of the method will be at least as fast, as well as more compact.
Proceedings ArticleDOI
ALI: A Procedural Language to Describe VLSI Layouts
TL;DR: ALI is a procedural language to specify VLSI layouts that does not need design rule checking, is easy to extend, facilitates the division of labor and permits the easy update of a layout to new design rules or to new processes.
Dissertation
Modeling and simulation of VLSI interconnections with moments
TL;DR: A new CAD simulation method for determining waveform estimates of MOS circuits is presented, which is particularly useful in determining the delay times and coupling noise voltages of interconnection networks.
References
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Proceedings ArticleDOI
Topological Analysis for VLSI Circuits
Paul Losleben,Kathryn Thompson +1 more
TL;DR: Algorithms are presented which use a bit map approach to derive connectivity checks, design rule checks, and electrical parameters for VLSI circuit artwork.
Proceedings ArticleDOI
Digital logic simulation at the gate and functional level
TL;DR: To keep simulation costs down and to avoid overwhelming the macroscopic features of a circuit with irrelevant data another level of digital logic simulation is required.
Proceedings ArticleDOI
CRITIC - an integrated circuit design rule checking program
TL;DR: CRITIC is a production proven design rule checking program which can perform minimum width, minimum clearance, minimum enclosure and other geometrical relationship tests for artwork figures on one mask level or between different mask levels.