C
Claude Basso
Researcher at IBM
Publications - 192
Citations - 3320
Claude Basso is an academic researcher from IBM. The author has contributed to research in topics: Network packet & Routing table. The author has an hindex of 29, co-authored 191 publications receiving 3311 citations. Previous affiliations of Claude Basso include University of Rochester & Cisco Systems, Inc..
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Patent
Longest prefix match lookup using hash function
TL;DR: In this article, a method and apparatus are used for finding the longest prefix match in a variable length prefix search when searching a direct table within a routing table structure of a network processor.
Patent
Method and system for performing a pattern match search for text strings
Claude Basso,Jean Calvignac,Philippe Damon,Gordon Taylor Davis,Marco C. Heddes,Clark Debs Jeffries +5 more
TL;DR: In this article, a search key is constructed by generating a full match search increment comprising the binary representation of a data string element, wherein the data string elements comprises all characters between a pair of delimiters.
Patent
Network communications for operating system partitions
Jean Calvignac,Claude Basso,Harvey Gene Kiel,Fabrice Jean Verplanken,Natarajan Vaidhyanathan,Ronald Edward Fuhs,Philippe Damon,Chih-Jen Chang,Alan Kyle Lucke,Colin Beaton Verrilli +9 more
TL;DR: In this article, the authors propose an apparatus for distributing network communications among multiple operating system partitions including a physical port allowing communications between the network and the computer system, and logical ports associated with the physical port, where each logical port is associated with one of the operating system partition.
Patent
Hop-by-hop flow control in an ATM network
TL;DR: In this article, a hop-by-hop backpressure mechanism is used to throttle the traffic entering a node exceeding a high threshold, generating stop backpressure primitives in order to throttle entering traffic.
Patent
Checkpointing mechanism for fault-tolerant systems
TL;DR: In this paper, the active and backup processors are coupled asynchronously with some hardware assist functions comprising a memory change detector which captures memory changes in the memory of the active processor and a mirroring control circuit which causes the memory changes when committed by establish recovery point signals generated by the active processors.