The objective of this paper is to give a comprehensive introduction to applied cryptography with an engineer or computer scientist in mind. The emphasis is on the knowledge needed to create practical systems which supports integrity, confidentiality, or authenticity. Topics covered includes an introduction to the concepts in cryptography, attacks against cryptographic systems, key use and handling, random bit generation, encryption modes, and message authentication codes. Recommendations on algorithms and further reading is given in the end of the paper. This paper should make the reader able to build, understand and evaluate system descriptions and designs based on the cryptographic components described in the paper.

[서평]「Applied Cryptography」

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[서평]「Computer Organization and Design, The Hardware/Software Interface」

In this paper, we propose a novel image encryption algorithm based on a hybrid model of deoxyribonucleic acid (DNA) masking, a Secure Hash Algorithm SHA-2 and the Lorenz system. Our study uses DNA sequences and operations and the chaotic Lorenz system to strengthen the cryptosystem. The significant advantages of this approach are improving the information entropy which is the most important feature of randomness, resisting against various typical attacks and getting good experimental results. The theoretical analysis and experimental results show that the algorithm improves the encoding efficiency, enhances the security of the ciphertext and has a large key space and a high key sensitivity, and it is able to resist against the statistical and exhaustive attacks.

A novel chaos-based image encryption using DNA sequence operation and Secure Hash Algorithm SHA-2

Color image DNA encryption using NCA map-based CML and one-time keys

This work proposes a processor architecture for elliptic curves cryptosystems over fields GF(2 m ) This is a scalable architecture in terms of area and speed that exploits the abilities of reconfigurable hardware to deliver optimized circuitry for different elliptic curves and finite fields The main features of this architecture are the use of an optimized bit-parallel squarer, a digit-serial multiplier, and two programmable processors Through reconfiguration, the squarer and the multiplier architectures can be optimized for any field order or field polynomial The multiplier performance can also be scaled according to system's needs Our results show that implementations of this architecture executing the projective coordinates version of the Montgomery scalar multiplication algorithm can compute elliptic curve scalar multiplications with arbitrary points in 021 msec in the field GF(2 167 ) A result that is at least 19 times faster than documented hardware implementations and at least 37 times faster than documented software implementations

A high-performance reconfigurable elliptic curve processor for GF(2m)

This work presents novel multipliers for Montgomery multiplication defined on binary fields GF(2m) Different to state of the art Montgomery multipliers, this work uses a linear feedback shift register (LFSR) as the main building block The authors studied different architectures for bit-serial and digit-serial Montgomery multipliers using the LFSR and the Montgomery factors xm and xm-1 The proposed multipliers are for different classes of irreducible polynomials: general, all one polynomials, pentanomials and trinomials The results show that the use of LFSRs simplifies the design of the multipliers architecture reducing area resources and retaining high performance compared to related works

/pdf/bit-serial-and-digit-serial-gf-2-m-montgomery-multipliers-36qdfjgv0o.pdf

Bit-serial and digit-serial GF(2 m )Montgomery multipliers using linear feedback shift registers

FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256

https://ccc.inaoep.mx/~rcumplido/papers/2014-Garcia-A%20Compact%20FPGA.pdf

A compact FPGA-based processor for the Secure Hash Algorithm SHA-256

We present a hardware architecture for an elliptic curve cryptography system performing the three basic cryptographic schemes: DH key generation, encryption and digital signature. The architecture is described by using hardware description languages, specifically Handel C and VHDL. Because of the sequential nature of the cryptographic algorithms, they are written in Handel C language. The critical part of the cryptosystem is a module performing the scalar multiplication operation. This module has been written in VHDL to let further improvements. The points of the elliptic curve are represented in projective coordinates working over the two-characteristic finite field and using polynomial basis. A prototype of this hardware architecture is implemented on a Xilinx Virtex II FPGA device.

/pdf/on-the-hardware-design-of-an-elliptic-curve-cryptosystem-4ngbawzbp5.pdf

On the hardware design of an elliptic curve cryptosystem

A linear sorter based on first in first out (FIFO) scheme is presented. It is capable of discarding the oldest value, inserting the incoming data while keeping the values sorted in a single clock cycle. This type of sorter can be used as coprocessor or as module in specialized architectures for order statistics filtering. The architecture is composed of identical processing elements thus can be easily adapted to any length according to specific application needs. The use of compact identical processing elements results in a high performance yet small architecture. Results of implementing the architecture on a field programmable gate array (FPGA) are presented and compared against other reported hardware based sorters.

/pdf/a-versatile-linear-insertion-sorter-based-on-a-fifo-scheme-20v5q5vho6.pdf

Claudia Feregrino-Uribe

Papers

Bit-serial and digit-serial GF(2 m )Montgomery multipliers using linear feedback shift registers

FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256

A compact FPGA-based processor for the Secure Hash Algorithm SHA-256

On the hardware design of an elliptic curve cryptosystem

A Versatile Linear Insertion Sorter Based on a FIFO Scheme