An error detecting and correcting system implementing the Reed-Solomon (1023, 1006) code having code words whose symbols are elements in the Galois field GF(210) generated by either the primitive polynomial x10 +x3 +1 or x10 +x7 +1. An original data word is encoded to produce a code word w(x) including a first set of checksum symbols appended thereto. Upon retrieval, the data symbols of the receive code word y(x) are encoded by the same encoder that encodes the original data word to produce a second set of checksum symbols. Both sets of checksum symbols are modulo-two summed to produce a residue R(x) from which error syndromes Si can be computed and thus enable rapid correction of errors in the received code word y(x). The system also monitors the number of non-zero symbols in the residue R(x) in order to avoid unnecessary computation of error syndromes Si and other decoding routines, such as when the received code word y(x) is otherwise uncorrectable or when the error exists only in the received checksum symbols, rather than in the data symbols. The distance between code words being (2T+ 2), the error correction routine is bypassed when the number of non-zero symbols in R(x) is less than or equal to T, which indicates that errors only reside in the checksum symbols. When the number of non-zero symbols equals (T+1), the error is uncorrectable. For determining whether a single error exists so that correction can quickly be made, the system also tests whether Si+1 /Si is constant for all error syndromes Si.

Multiple error detecting and correcting system employing Reed-Solomon codes

A codec consists of an encoder and decoder. The encoder provides 12 information bits, 11 parity bits generated according to the polynomial for the (23, 12) Golay code, and an overall parity bit to a transmitter at selected transmit times to form a 24-bit block of data. The decoder is separated into two independent list decoders, a comparator, and common clock generator and output buffers. Each list decoder is divided into a syndrome generator and an overall parity check generator, a syndrome error pattern table, an input buffer, error correction logic, and four-error detection logic. The error pattern table includes a pair of read only memories storing the most likely 12-bit error patterns at each ROM address corresponding to each syndrome. An additional 4-bit output is used to indicate the number of errors in the associated error pattern. The comparator compares the number of errors detected in the two independent decoders and chooses the decoder having the fewer number of errors to provide the corrected data.

Weighted erasure codec for the (24, 12) extended Golay code

The polynomial operator in the Galois field of the invention is organized at three levels: a multiplexer level to select and transmit the operands to be used for the successive stage of the calculation to a second level; a so-called pipeline level comprising 3 flip-flop registers to memorize the operands selected at the first level; a third level for calculation, comprising a multiplier-adder which has its inputs X, Y and Z connected to the outputs of the registers, and which gives the coefficients of the resultant polynomials in the Galois field while always performing the same calculation by repetition of the same control instruction. This operator can be applied to digital telecommunications for the encoding and decoding of BCH or RS (REED SOLOMON) error-correcting codes, and can be used to make an integrated processor capable of processing digital data in the form of octets.

Polynomial operator in galois fields and a digital signal processor comprising an operator of this type

A system for detecting multiple errors that may occur during transfer of data and for correcting up to two of these errors simultaneously. The system has a component for calculating a number of check bits associated with the data word. Also provided is a component for grouping all data bits into base groups and multiple groups, the sum of the number of base groups and multiple groups being equal to the number of check bits. Up to two weights are assigned for each data bit. The system distributes the data bits among the groups according to the weights assigned thereto. Also provided is a component for generating a check bit for each of the groups and for padding the data word with the check bits to form an appended data word. A generator creates a predetermined number of syndrome bits, the number being the number of check bits. Finally, a decoder is provided for decoding the syndrome bits to identify the erroneous bits in the data word.

System for multiple error detection with single and double bit error correction

Disclosed are an error-detecting encoding apparatus for creating parity bits by error-detecting encoding processing, appending the parity bits to an input data string and encoding the data string, and an error-detecting decoding apparatus for detecting error using these parity bits. Data segmenting means segments an input data string, which is to undergo error-detecting encoding, into a plurality of sub-data strings, dividing means divides the segmented sub-data strings by a polynomial, which is for generating an error-detecting code, and calculates remainders, converting means applies conversion processing, which conforms to a segmentation position of the sub-data strings, to the remainders on a per-remainder basis, and combining means combines converted values, which have been obtained by the conversion processing, and outputs parity bits. An encoder appends this parity to a data string, and a decoder detects error using this parity.

Error-detecting encoding and decoding apparatus and dividing apparatus

A single and double error correction and triple detection system using cyclical redundancy codes based on the generator polynomials: G(1171) = X.sup.9 + X.sup.6 + X.sup.5 + X.sup.4 + X.sup.3 + 1 g(1513) = x.sup.9 + x.sup.8 + x.sup.6 + x.sup.3 + x + 1.

Clement E. Burghard

Papers

High speed double error correction plus triple error detection system