Patent
High speed double error correction plus triple error detection system
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TLDR
A single and double error correction and triple detection system using cyclical redundancy codes based on the generator polynomials: G(1171) = X.sup.9 + X.8 + x.6 + X as mentioned in this paper.Abstract:
A single and double error correction and triple detection system using cyclical redundancy codes based on the generator polynomials: G(1171) = X.sup.9 + X.sup.6 + X.sup.5 + X.sup.4 + X.sup.3 + 1 g(1513) = x.sup.9 + x.sup.8 + x.sup.6 + x.sup.3 + x + 1.read more
Citations
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Patent
Multiple error detecting and correcting system employing Reed-Solomon codes
TL;DR: In this article, an error detecting and correcting system implementing the Reed-Solomon (1023, 1006) code having code words whose symbols are elements in the Galois field GF(210) generated by either the primitive polynomial x10 +x3 +1 or x10+x7 +1.
Patent
Weighted erasure codec for the (24, 12) extended Golay code
Ming-I. Weng,Lin-nan Lee +1 more
TL;DR: In this article, an encoder and decoder are separated into two independent list decoders, a comparator, and common clock generator and output buffers, each list decoder is divided into a syndrome generator and an overall parity check generator, a syndrome error pattern table, an input buffer, error correction logic, and four-error detection logic.
Patent
Polynomial operator in galois fields and a digital signal processor comprising an operator of this type
TL;DR: The polynomial operator in the Galois field of the invention is organized at three levels: a multiplexer level to select and transmit the operands to be used for the successive stage of the calculation to a second level; a so-called pipeline level comprising 3 flip-flop registers to memorize the selected operands selected at the first level; and a third level for calculation, comprising a multiplier-adder which has its inputs X, Y and Z connected to the outputs of the registers, and which gives the coefficients of the resultant polynomials.
Patent
System for multiple error detection with single and double bit error correction
TL;DR: In this article, a system for detecting multiple errors that may occur during transfer of data and for correcting up to two of these errors simultaneously is presented, where the system has a component for calculating a number of check bits associated with the data word.
Patent
Error-detecting encoding and decoding apparatus and dividing apparatus
TL;DR: In this paper, an error-detecting encoding apparatus for creating parity bits by creating a parity bit by decoding the input data string and encoding the data string, and a decoding apparatus for detecting error using these parity bits.
References
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Patent
Table lookup direct decoder for double-error correcting (DEC) BCH codes using a pair of syndromes
TL;DR: In this paper, an approach for directly decoding and correcting double-bit random errors per word and detecting triple-bit error per word is presented. But this approach is not suitable for the decoding of large numbers of words.
Patent
Apparatus and method for a memory partial-write of error correcting encoded data
Chester M. Nibby,John C Manton +1 more
TL;DR: In this article, the error-correcting code check bits for the combined data group while simultaneously verifying the accuracy of the previously stored data group are determined. But the correction of the error check bits is not considered.
Patent
Triple track error correction
TL;DR: In this paper, a method for correcting errors in up to three tracks or channels in a multi-track data system is provided, where message data is formed into a codeword by adding three check bytes which are dependent on each other and are generated from the information bytes.
Patent
Apparatus for detecting and correcting errors in digital information organized into a parallel format by use of cyclic polynomial error detecting and correcting codes
TL;DR: In this paper, it was shown that cyclic polynomial error correcting codes can be implemented in a serial fashion by a feed-back shift register type of encoder and decoder.
Patent
Double error correcting method and system
Hong Se June,Arvind M. Patel +1 more
TL;DR: In this article, a cyclic code is encoded for double error correction in accordance with the following parity check matrix: where the code length N is given by 2M-1 and Alpha is a prime element of GF(2m) represented by a binary column vector.