High-performance parallel computer architecture and systems have been improved at a phenomenal rate. In the meantime, VLSI computer-aided design (CAD) software for multibillion-transistor IC design has become increasingly complex and requires prohibitively high computational resources. Recent studies have shown that, numerous CAD problems, with their high computational complexity, can greatly benefit from the fast-increasing parallel computation capabilities. However, parallel programming imposes big challenges for CAD applications. Fully exploiting the computational power of emerging general-purpose and domain-specific multicore/many-core processor systems, calls for fundamental research and engineering practice across every stage of parallel CAD design, from algorithm exploration, programming models, design-time and run-time environment, to CAD applications, such as verification, optimization, and simulation. This journal special section will cover recent progress on parallel CAD research, including algorithm foundations, programming models, parallel architectural-specific optimization, and verification. More specifically, papers with in-depth and extensive coverage of the following topics will be considered, as well as other topics relevant to the design of parallel CAD algorithms and software tools. 1. Parallel algorithm design and specification for CAD applications 2. Parallel programming models and languages of particular use in CAD 3. Runtime support and performance optimization for CAD applications 4. Parallel architecture-specific design and optimization for CAD applications 5. Parallel program debugging and verification techniques particularly relevant for CAD The papers should be submitted via the Manuscript Central website and should adhere to standard ACM TODAES formatting requirements (http://todaes.acm.org/). The page count limit is 25.

Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems

Early routability prediction helps designers and tools perform preventive measures so that design rule violations can be avoided in a proactive manner. However, it is a huge challenge to have a predictor that is both accurate and fast. In this work, we study how to leverage convolutional neural network to address this challenge. The proposed method, called RouteNet, can either evaluate the overall routability of cell placement solutions without global routing or predict the locations of DRC (Design Rule Checking) hotspots. In both cases, large macros in mixed-size designs are taken into consideration. Experiments on benchmark circuits show that RouteNet can forecast overall routability with accuracy similar to that of global router while using substantially less runtime. For DRC hotspot prediction, RouteNet improves accuracy by 50% compared to global routing. It also significantly outperforms other machine learning approaches such as support vector machine and logistic regression.

https://dl.acm.org/doi/pdf/10.1145/3240765.3240843

RouteNet: routability prediction for mixed-size designs using convolutional neural network

The ISPD~2015 placement-contest benchmarks include all the detailed pin, cell, and wire geometry constraints from the 2014 release, plus(a) added fence regions and placement blockages,(b) altered netlists including fixed macro blocks,(c) reduced standard cell area utilization via larger floorplan outlines, and(d)] specified upper limits on local cell-area density.Compared to the 2014 release, these new constraints add realism and increase the difficulty of producing detail-routable wirelength-driven placements.

ISPD 2015 Benchmarks with Fence Regions and Routing Blockages for Detailed-Routing-Driven Placement

The Nesterov’s method approach to analytic placement has recently demonstrated strong solution quality and scalability. We dissect the previous implementation strategy and show that solution quality can be significantly improved using two levers: 1) constraint-oriented local smoothing and 2) dynamic step size adaptation. We propose a new density function that comprehends local overflow of area resources; this enables a constraint-oriented local smoothing at per-bin granularity. Our improved dynamic step size adaptation automatically determines step size and effectively allocates optimization effort to significantly improve solution quality without undue runtime impact. Our resulting global placement tool, RePlAce, achieves an average of 2.00% half-perimeter wirelength (HPWL) reduction over all best known ISPD-2005 and ISPD-2006 benchmark results, and an average of 2.73% over all best known modern mixed-size (MMS) benchmark results, without any benchmark-specific code or tuning. We further extend our global placer to address routability, and achieve on average 8.50%–9.59% scaled HPWL reduction over previous leading academic placers for the DAC-2012 and ICCAD-2012 benchmark suites. To our knowledge, RePlAce is the first work to achieve superior solution quality across all the ISPD-2005, ISPD-2006, MMS, DAC-2012, and ICCAD-2012 benchmark suites with a single global placement engine.

RePlAce: Advancing Solution Quality and Routability Validation in Global Placement

Existing routability-driven placers mostly employ rudimentary and often crude congestion models that fail to account for the complexities in modern designs, e.g., the impact of non-uniform wiring stacks, layer directives, partial and/or complete routing blockages, etc. In addition, they are hampered by congestion metrics that do not accurately score or represent design congestion. This is in large part due to the non-availability of public designs depicting industrial wiring stacks and other complexities affecting design routability. The aim of the DAC 2012 routability-driven placement contest is to address these issues, by way of the following: (a) release challenging benchmark designs that are derived from modern industrial ASICs, and contain information to perform both placement and routing, (b) present a new congestion metric, as well as an accurate congestion analysis framework to evaluate and compare the routability of various placement algorithms. We hope that a set of challenging benchmarks, along with a standard, publicly available evaluation framework will further advance research in routability-driven placement.

The DAC 2012 routability-driven placement contest and benchmark suite

On behalf of the organizing committee, we are delighted to welcome you to the 2013 ACM International Symposium on Physical Design (ISPD), held at the Ridge Tahoe Resort in Stateline, Nevada. Continuing the great tradition established by its twenty-one predecessors, which includes a series of five ACM/SIGDA Physical Design Workshops held intermittently in 1987-1996 and sixteen editions of ISPD in the current form since 1997, the 2013 ISPD provides a premier forum to present leading-edge research results, exchange ideas, and promote research on critical areas related to the physical design of VLSI and other related systems.

We received 57 submissions from all around the world. After a rigorous, month-long, double-blind review process, the Technical Program Committee (TPC) met face-to-face to select papers to be included in the technical program based on over 250 reviews provided by 21 TPC members and 56 external reviewers. Finally, mthe committee accepted 17 papers to be presented in the symposium. These papers exhibit latest advancements in floorplanning, clocking, placement as well as routing, address challenges in advanced processes, identify opportunities in emerging technologies such as VeSFET, biochips, and e-beam, and offer new 3D solutions for physical design.

The ISPD 2013 program is complemented by a ISPD keynote speech as well as a TAU/ISPD joint keynote speech, thirteen ISPD invited talks, and five TAU/ISPD joint invited talks, all of which are delivered by distinguished researchers in both industry and academia. Mr. Liam Madden, corporate vice president of FPGA development and silicon technology at Xilinx, will present in the keynote speech future directions of next generation 3D technologies. A commemorative session on Monday afternoon allows us to pay tributes to Professor Yoji Kajitani, one of the most influential pioneers in EDA and a great educator. His collaborators and former students will share with us Professor Kajitani's exceptional works in graph theory and their applications to rectangle packing as well as place-and-route, and his recent research in the area of beyond-die co-design and integration. Professor Kajitani will conclude the commemoration session with a talk about how the concept of permutation links the problems in channel routing, packing, placement, and various other PD areas. Other invited talks will be interspersed with the presentations of accepted papers. The topics covered include the impacts of electromigration on PD, debug, verification and test, lithography advancement and challenges in the advanced technology nodes, new breakthroughs in synchronous designs, system-level PD, and next generation device design and architectures.

This year, we are happy to announce 3 joint sessions with the International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU). The joint sessions have extended the technical program of ISPD by half a day. The joint TAU/ISPD keynote, given by Dr. Ruchir Puri, IBM fellow and adjunct professor at Columbia University, showcases the challenges and opportunities in EDA for high-performance microprocessors. We are excited to have a joint TAU/ISPD session dedicated to both the ISPD's discrete gate sizing contest and TAU's variability aware timing analysis contest. On Wednesday afternoon, there is a special joint invited session on hierarchical PD and timing.

Another special addition to ISPD's program in 2013 is the Expert Designer/User Session (EDS), which contains six invited presentations followed by a poster session. All EDS speakers are carefully selected to cover a wide range of PD topics. This brings the perspectives from the designer/user community to PD researchers, and encourages discussions and future research collaborations.

Since 2005, ISPD has organized highly competitive contests to promote and advance research in placement, global routing, clock network synthesis, and discrete gate sizing. This year's discrete gate sizing contest, which includes realistic interconnect delay calculation, continues to attract a large number of participants from all over the world. The contest results will be announced by the ISPD Contest Chair on Wednesday morning. Continuing the tradition of all the past contests, a new large-scale real-world benchmark suite for gate sizing with discrete gate library will be released in ISPD website: http://www.ispd.cc

Proceedings of the 2013 ACM International symposium on Physical Design

Based on a simple intuitive notion, in this paper, we propose an efficient post-placement improvement scheme. Based on the given timing slack distribution of a circuit, a corresponding “slack mountain map” can be visualized with peaks representing most violating (negative) slacks and valleys representing non-critical (positive) slacks respectively. Guided by this map, violating paths are eliminated or improved when slack mountains are flattened by applying a local logic perturbation technique (rewiring) iteratively to shift logic resources from critical to non-critical areas. Due to the locality property of the rewiring technique, to better avoid being stuck at local minimums, instead of running rewiring operations from the peak top towards lower areas, we do this local logic shifting starting from “sea areas” (most non-critical) towards peak (most critical) areas. At the end, as the slack map is more flattened, a circuit with slack violations more evenly distributed can be yielded. Comparing to the recent work [1], our experimental results demonstrate that this scheme can obtain a better or comparable delay reduction but with CPU time one order of magnitude smaller.

Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths

Techniques are disclosed for providing a break reminder in a multi-device and multi-user environment. A management service monitors usage activity of one or more devices by a first user in a plurality of users. Each of the one or more devices is associated with the first user. An amount of weighted use time of each user on one or more devices (from a first point in time to a second point in time) is determined based on the usage activity. Upon determining that the amount of time exceeds a specified threshold amount of time, the management service generates a break reminder. The management service sends the break reminder to at least one of the one or more devices currently being used.

Techniques for providing a seamless break reminder in the multi-device and multi-user environment

This paper presents WRIP - a Wirelength-driven Rewiring-based Incremental Placement which effectively reduces wirelength of the optimized placement of industrial large-scale standard cell designs. WRIP uses a powerful logic synthesis technique called logic rewiring which restructures the local circuits while preserving the logic functionality and reduces the wirelength under an accurate estimation of the half perimeter wirelength (HPWL) metric. We integrated WRIP into an industrial EDA tool and tested it upon several real designs with hundreds of thousands of movable objects. Tested on circuits which has been fully optimized by the state-of-the-art industrial placement tool, our experiments showed that on average WRIP reduces wirelength by 2.25% after placement and 2.45% after global routing in HPWL and Steiner WL model respectively. The runtime of WRIP is only about half an hour for the largest tested ASIC circuit. This is the first attempt to fully integrate powerful logic synthesis into industrial placement tools with real-life effectiveness and efficiency.

WRIP: logic restructuring techniques for wirelength-driven incremental placement

The clock distribution network presents one of the most important design challenges in high-performance synchronous VLSI designs. However, automation in clock network synthesis is usually limited to local clock domains for two main reasons. (1) Global clock is too important for designers to take the risk of adopting a fully automated clocking flow. (2) Unlike in other EDA areas (such as synthesis/placement/routing), clock synthesis tools are highly tied to clock network topologies, ground/power planning, clock gating, macro floorplanning, clocking methodologies, etc. It is thus very difficult to implement a set of generic clock synthesis tools for design productivity considerations. That being said, industrial clocking methodologies usually resort to overdesigning because clock synthesis is just too critical to fail.

Cliff Sze

Papers

Proceedings of the 2013 ACM International symposium on Physical Design

Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths

Techniques for providing a seamless break reminder in the multi-device and multi-user environment

WRIP: logic restructuring techniques for wirelength-driven incremental placement

The future of clock network synthesis