A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by tracking system usage, manifested by read and write commands issued to the memory module, or by measuring temperature changes indicating a level of device activity beyond normal refresh activity. Alternatively, measured activity levels can be transmitted over a system bus to a centralized power management controller which, responsive to the activity level packets transmitted by remote memory modules, direct devices of those remote memory modules to a reduced power state. The centralized power management controller could be disposed on a master memory module or in a memory or system controller.

System and method for selective memory module power management

A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.

Reconfigurable memory module and method

A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory (“SDRAM”) devices. The memory hub includes a processor interface coupled to the processor and a plurality of memory interfaces coupled to respective SDRAM devices. The processor interface is coupled to the memory interfaces by a switch. Each of the memory interfaces includes a memory controller, a cache memory, and a prediction unit. The cache memory stores data recently read from or written to the respective SDRAM device so that it can be subsequently read by processor with relatively little latency. The prediction unit prefetches data from an address from which a read access is likely based on a previously accessed address.

Memory hub with internal cache and/or memory access prediction

Apparatus and associated methods for improving I/O performance in a computing system which includes one or more MPUs and one or more IOPs. I/O requests are queued by a requesting MPU in a memory shared with one or more IOPs. Each IOP is associated with a queue. Each IOP may continue processing queued I/O requests after completing processing on an earlier request. In addition, each MPU is associated with a queue shared with the IOPs. When an IOP completes processing of an I/O request, a completion message is added to the requesting MPU's queue and an interrupt is generated for that MPU. The MPU services all completion messages in its queue when the interrupt is processed. A threshold value is associated with each MPU queue. The threshold value indicates the minimum number of completed I/O requests required before an interrupt request is generated to the MPU. The threshold value for each MPU may be tuned to permit the computing system to balance the need for rapid I/O response time with the need for reduced interrupt overhead processing in the MPU. Various physical embodiments of the invention are disclosed wherein the queue is located in either a shared memory or in a register file. Additionally, various embodiments separate the queue used to store new I/O requests from the queue used to store completion messages while other embodiments merge the two queuing functions into a single queue where each entry contains an I/O request with a completion status field.

Employing request queues and completion queues between main processors and I/O processors wherein a main processor is interrupted when a certain number of completion messages are present in its completion queue

A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub includes a link interface for receiving memory requests for access to memory devices of the memory system and a memory device interface coupled to the memory devices for coupling memory requests to the memory devices. A memory hub diagnostic engine is coupled through a switch to the link interface and the memory device interface to perform diagnostic testing of the memory system. The diagnostic engine includes a maintenance port that provides access to results of the diagnostic testing and through which diagnostic testing commands can be received.

System and method for on-board diagnostics of memory modules

Described is a technique which finds use in transferring data between system memory which is arranged in pages and an attached storage system. In such a paged memory, data which crosses pages having contiguous virtual addresses may map to data which crosses discontiguous physical pages. Scatter-gather is advantageously employed in such a system in order to achieve the transfer data directly between memory and storage usually by Direct Memory Access (DMA). A secondary storage device which supports scatter-gather usually includes hardware which will perform the necessary calculations to transfer the data to and from the correct locations in physical memory. The technique of the present invention is useful with storage systems that do not support scatter-gather and comprises determining for each data transfer the identity of any requested sector which lies completely within a physical page and the identity of any sector which crosses boundaries between discontiguous physical pages; and for those sectors which lie within a physical page, transferring the sectors directly between secondary storage and memory by DMA; and for those sectors which cross said boundaries, transferring each sector to either the memory or secondary storage via an intermediate buffer.

Scatter-gather in data processing system

A cache system is described which is adapted for staging data between host memory and a disk array comprising a plurality of disk storage devices plus associated controller unit, data being storable across the disks of the array in the form of strides, each stride comprising a multi-sector `stripe` of data on each of two or more devices of the array and an associated multi-sector parity block on a further array device. The cache system includes means for linking the data and associated parity making up a stride within the cache as a cache data unit which is manipulated in the cache as a single entity. References from the host to data held within the cache causes the referenced cache unit to move to the head of a list of cache units. Using such a cache system, when a cache unit at the bottom of the list is committed to disk, there is an increased likelihood that most or all the data making up a stride will be in the cache and therefore the number of redundant accesses to the disk needed to generate parity data will be reduced or eliminated.

System and method for managing data in a cache system for a disk array

A cache system is described which is adapted for staging data between host memory and a disk array comprising a plurality of disk storage devices plus associated controller unit, data being storable across the disks of the array in the form of strides, each stride comprising a multi-sector 'stripe' of data on each of two or more devices of the array and an associated multi-sector parity block on a further array device. The cache system includes means for linking the data and associated parity making up a stride within the cache as a cache data unit which is manipulated in the cache as a single entity. References from the host to data held within the cache causes the referenced cache unit to move to the head of a list of cache units. Using such a cache system, when a cache unit at the bottom of the list is committed to disk, there is an increased likelihood that most or all the data making up a stride will be in the cache and therefore the number of redundant accesses to the disk needed to generate parity data will be reduced or eliminated.

Clive Scott Oldfield

Papers

Scatter-gather in data processing system

System and method for managing data in a cache system for a disk array

Cache system for disk array