An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Top layers of metal for high performance IC's

A device and methods of forming an interconnection within a prepatterned channel in a semiconductor device are described. The present invention includes a method of forming an interconnect channel within a semiconductor device. A first dielectric layer is deposited over a substrate and patterned to form a contact opening that is subsequently filled with a contact plug. A second dielectric layer is deposited over the patterned first dielectric layer and the contact plug. The second dielectric layer is patterned to form the interconnect channel, wherein the first dielectric layer acts as an etch stop to prevent etching of the substrate. The present invention also includes a method of forming an interconnect. A dielectric layer is deposited over a substrate and patterned to form an interconnect chapel. A metal layer is deposited over the patterned dielectric layer and within the interconnect channel. The metal layer is polished with an alkaline solution to remove the metal layer that does not lie within the interconnect chapel to form an interconnect. The present invention further includes a method of forming an interconnect over a silicon nitride layer. The silicon nitride layer is deposited over a semiconductor substrate and patterned to form a contact opening that is subsequently filled with a conductive material. A metal layer is deposited on the patterned silicon nitride layer and the contact plug and patterned to form the interconnect such that all of the interconnect lies on the contact plug and part of the patterned silicon nitride layer.

Methods of forming an interconnect on a semiconductor substrate

A process is disclosed which applies advanced concepts of Z-technology to the field of dense electronic packages. Starting with standard chip-containing silicon wafers, modification procedures are followed which create IC chips having second level metal conductors on top of passivation (which covers the original silicon and its aluminum or other metallization). The metal of the second level conductors is different from, and functions better for electrical conduction, than the metallization included in the IC circuitry. The modified chips are cut from the wafers, and then stacked to form multi-layer IC devices. A stack has one or more access planes. After stacking, and before applying metallization on the access plane, a selective etching step removes any aluminum (or other material) which might interfere with the metallization formed on the access plane. Metal terminal pads are formed in contact with the terminals of the second level conductors on the stacked chips. The pads and terminals are formed of the same metallic material in order to maximize T-connection conducting efficiency.

Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting

A process for filling high aspect ratio gaps on substrates uses conventional high density plasma deposition processes while reducing the concentration of the inert gas, such as Ar, to 0-13% of the total process gas flow. By reducing the inert gas concentration, sputtering or etching is reduced, resulting in reduced sidewall deposition from the sputtered material. Consequently, gaps with aspect ratios of 3.0:1 and higher can be filled without the formation of voids and without damaging circuit elements.

High aspect ratio gapfill process by using HDP

Accelerated life data are presented on several integratedcircuit metallization systems including Al, Mo-Au, Ti-Pt-Au, and a new system Ti: W-Au where the RF sputtered Ti: W layer is a pseudo alloy of 10-20 percent Ti in W. Life tests include total water immersion, high-pressure steam and 85°C/85 percent RH/bias on bare and plastic-encapsulated devices. Heat-age and resistivity-ratio data are presented showing the metallurgical stability of the Ti: W-Au system. The corrosion resistance decreases as Ti-Pt-Au > Ti: W-Au >> Mo-Au ? Al.

Corrosion Resistance of Several Integrated-Circuit Metallization Systems

An improved method of forming interconnections on a semiconductor slice in which a barrier metal of TI:W or Ta is deposited followed by deposit of a conducting layer and then a masking layer of Ta after which the masking layer is patterned with photo-resist and plasma etched whereupon the conducting layer is sputter etched with the barrier layer then being removed to provide an interconnecting lead with sloping sides over which insulation and a second level of metallization may be applied without danger of problems at crossovers.

Method of contacting and connecting semiconductor devices in integrated circuits

Platinum thin-film metallization is selectively etched with aqua regia, using a chromium or titanium film as an etch-resistant mask. In a specific embodiment, an integrated circuit structure is metallized with successive layers of titanium, platinum, gold and a metal selected from molybdenum, tungsten, rhenium and corrosion-resistant alloys thereof. The system is particularly suited for the formation of insulated ''''cross-over'''' metallization, or multi-level interconnecting metallization.

Platinum thin-film metallization method

Refractory metals, refractory metal silicide, and polysilicon/refractory metal silicide sandwich structures integrated circuits are etched using carbonyl chemistry. That is, the deposited material is plasma etched using an etchant gas mixture which contains a gas, such as CO2, which can dissociate to provide carbonyl groups (CO) or, in combination with halogen sources, carbonyl halide radicals.

Plasma etching of refractory metals and their silicides

A process has been developed for fabricating a nonpolar low loss thin film capacitor utilizing tantalum oxide for high capacitance per unit area as a dielectric which is deposited in film form relative to a suitable substrate. A counter electrode is deposited on a substrate. A film of metal having a high recrystallization temperature is deposited on the counter electrode. This deposition forms the bottom electrode of the capacitor structure. The metal film has a quality thermal expansion resistance and a high reliability in thermal environments.

Clyde R. Fuller

Papers

Corrosion Resistance of Several Integrated-Circuit Metallization Systems

Method of contacting and connecting semiconductor devices in integrated circuits

Platinum thin-film metallization method

Plasma etching of refractory metals and their silicides

Method for fabricating a thin film capacitor