A device and methods of forming an interconnection within a prepatterned channel in a semiconductor device are described. The present invention includes a method of forming an interconnect channel within a semiconductor device. A first dielectric layer is deposited over a substrate and patterned to form a contact opening that is subsequently filled with a contact plug. A second dielectric layer is deposited over the patterned first dielectric layer and the contact plug. The second dielectric layer is patterned to form the interconnect channel, wherein the first dielectric layer acts as an etch stop to prevent etching of the substrate. The present invention also includes a method of forming an interconnect. A dielectric layer is deposited over a substrate and patterned to form an interconnect chapel. A metal layer is deposited over the patterned dielectric layer and within the interconnect channel. The metal layer is polished with an alkaline solution to remove the metal layer that does not lie within the interconnect chapel to form an interconnect. The present invention further includes a method of forming an interconnect over a silicon nitride layer. The silicon nitride layer is deposited over a semiconductor substrate and patterned to form a contact opening that is subsequently filled with a conductive material. A metal layer is deposited on the patterned silicon nitride layer and the contact plug and patterned to form the interconnect such that all of the interconnect lies on the contact plug and part of the patterned silicon nitride layer.

Methods of forming an interconnect on a semiconductor substrate

A method for forming interconnections for semiconductor fabrication and semiconductor devices have such interconnections are described. A first patterned dielectric layer is formed over a semiconductor substrate and has a first opening filed with conductive material. Another patterned dielectric layer is formed over the first dielectric layer and has a second opening over at least a portion of the conductive material. The first patterned dielectric layer may serve as an etch-stop in patterning the other patterned dielectric layer. Also, a dielectric etch-stop layer may be formed over the first patterned dielectric layer and over the conductive material before the other patterned dielectric layer has been formed. This dielectric etch-stop layer may serve as an etch-stop in patterning the other patterned dielectric layer. The second opening exposes a portion of the dielectric etch-stop layer. The exposed portion of the dielectric etch-stop layer is removed. The second opening is filled with conductive material.

Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections

A method for manufacturing sidewall contacts for a chalcogenide memory device is disclosed. A first conductive layer is initially deposited on top of a first oxide layer. The first conductive layer is then patterned and etched using well-known processes. Next, a second oxide layer is deposited on top of the first conductive layer and the first oxide layer. An opening is then etched into at least the first oxide layer such that a portion of the first conductive layer is exposed within the opening. The exposed portion of the first conductive layer is then removed from the opening such that the first conductive layer is flush with an inner surface or sidewall of the opening. After depositing a chalcogenide layer on top of the second oxide layer, filling the opening with chalcogenide, a second conductive layer is deposited on top of the chalcogenide layer.

Method for manufacturing sidewall contacts for a chalcogenide memory device

A method for forming interconnections for semiconductor fabrication and semiconductor devices have such interconnections are described. A first patterned dielectric layer is formed over a semiconductor substrate and has a first opening filled with conductive material. Another patterned dielectric layer is formed over the first dielectric layer and has a second opening over at least a portion of the conductive material. The first patterned dielectric layer may serve as an etch-stop in patterning the other patterned dielectric layer. Also, a dielectric etch-stop layer may be formed over the first patterned dielectric layer and over the conductive material before the other patterned dielectric layer has been formed. This dielectric etch-stop layer may serve as an etch-stop in patterning the other patterned dielectric layer. The second opening exposes a portion of the dielectric etch-stop layer. The exposed portion of the dielectric etch-stop layer is removed. The second opening is filled with conductive material.

Method for forming multileves interconnections for semiconductor fabrication

Polyimide insulators for multilevel interconnections

A process has been developed for fabricating a nonpolar low loss thin film capacitor utilizing tantalum oxide for high capacitance per unit area as a dielectric which is deposited in film form relative to a suitable substrate. A counter electrode is deposited on a substrate. A film of metal having a high recrystallization temperature is deposited on the counter electrode. This deposition forms the bottom electrode of the capacitor structure. The metal film has a quality thermal expansion resistance and a high reliability in thermal environments.

Method for fabricating a thin film capacitor

A microelectronic integrated circuit having first and second levels of thin-film metallization separated by an insulation layer is provided with a system for electrical interconnections between metallization levels, at selected locations, without requiring extra spacing between metal paths, in either the first or second levels. Maximum circuit density is thereby permitted, with no restriction on the placement of interconnection vias. Circuit layout is greatly simplified because all metal paths have uniform widths and minimum spacings, achieved with the use of vias that are "oversized" in both the transverse and longitudinal directions. Consequently, it is required that second level metal differ in composition from first level metal, and be patterned with an etchant that does not attack first level metal.

Maximum density interconnections for large scale integrated circuits

The reliability of the 2-level aluminum/silicon dioxide/aluminum system has been investigated. Test structures were fabricated using two types of aluminum films, deposited on unheated substrates (Al-I) and on 200°C substrates (Al-II). Two types of insulation layers were used: SiO2 from oxidation of silane, and rf sputtered SiO2 with an overlay of silane SiO2. Scanning electron microscopy was used to examine the topography of the crossovers and via-holes. More hillocks were seen with Al-I films than with Al-II films. Via-hole resistance and the incidence of intralevel opens and interlevel shorts were determined. A comparative evaluation of the four structures indicated that Al-II films are more desirable for first-level metallization. The test structures with Al-II films, subjected to 150°C storage for 1000 hours, exhibited no increase in the interlevel resistance and a failure rate of one interlevel short per 12000 crossovers, each 0.5 mil (13 ?m) square. Temperature cycling of these structures from -65°C to 150°C for 500 cycles developed no interlevel shorts and resulted in a decrease of the interlevel resistance. These observations show a failure rate of less than one interlevel short per 13200 crossovers in 500 cycles. Process problems related to the reliability of 2-level structures are discussed.

Prabhakar B. Ghate

Papers

Method for fabricating a thin film capacitor

Maximum density interconnections for large scale integrated circuits

Reliability Studies on the 2-Level Al/SiO2/Al System