An analog-to-digital conversion circuit is described which includes a front end sigma-delta modulator circuit, a multi-stage digital decimation filter circuit, and a digital compensation filter circuit. An overrange detect circuit is also provided.

Delta-sigma ADC with multi-stage decimation filter and gain compensation filter

Disclosed is a method in a disk drive that allows the functionality of a single high-resolution DAC to be replicated with a pair of lower-resolution DACs that are operated in a unique manner that provides monotonic behavior and reduces both differential and integral non-linearity. The two lower-resolution DACs take up substantially less space that one higher-resolution DAC when implemented in a semiconductor die. The method combines coarse values from one DAC with fine values from the other DAC to form a combined analog output signal within operational segments that collectively span a range of N-bit demands. The method operates such the operational segments overlap one another by 50 percent, with an endpoint of each operational segment ending near a center of an overlapped operational segment. The method's overlapping relationship tends to cause the combined analog output voltage to vary monotonically, by maintaining the X-bit command and only varying the Y-bit command whenever possible for small changes in the combined analog output signal.

Method of using two low-resolution DACS for converting high-resolution digital demands into analog output signals that monotonically drive an actuator motor in a disk drive

Systems, methods, and integrated circuits employ switch capacitor technology for digital to analog conversion. In one embodiment a DAC receives a multi-bit digital signal. The DAC has a switch capacitor network with a plurality of sub DACs. Each of the sub DACs receives an associated bit of the multi-bit digital signal. The capacitance within each of the sub DACs receives an amount of charge in response to the associate bit. At least two of the sub DACs share charge with one another, and the network outputs at least one analog signal indicative of a sum of values of each bit in the multi-bit digital signal.

Method and apparatus for use in switched capacitor systems

In this thesis we present an overview and study on digital-to-analog converters (DAC), mainly for communications applications. Especially, we look at some digital subscriber line (DSL) specificatio ...

Studies on CMOS Digital-to-Analog Converters

A multibit /spl Delta/-/spl Sigma/ modulator is an attractive way of realizing a high-accuracy, high-speed, and low-power data converter. However, the overall resolution of the modulator is determined by the internal digital-to-analog conversion (DAC) linearity. Methods for high-order noise shaping, noise-shaping dynamic element matching (NSDEM), have been proposed in order to overcome this drawback. However, a real implementation has not been realized until now. This paper presents the actual circuit configuration of a tree-structured NSDEM (TNSDEM) technique, which is applied to a multibit /spl Delta/-/spl Sigma/ DAC and analog-to-digital converter (ADC) using a nine-level internal DAC. This is the first report of a /spl Delta/-/spl Sigma/ ADC and DAC using the second-order NSDEM method. The test chip of the third-order /spl Delta/-/spl Sigma/ ADC realizes a signal bandwidth of 100 kHz and a dynamic range of 79 dB in the ADC and 80 dB in the DAC. The test chip only consumes 9.6 mW in the ADC and 5.2 mW in the DAC with a 2.7 V power supply.

A third-order /spl Delta/-/spl Sigma/ modulator using second-order noise-shaping dynamic element matching

A tree structure for the efficient implementation of segment selection in a multibit oversampled DAC is presented. The structure offers high-order noise-shaping of mismatch errors without the use of vector quantisation and so can be implemented in low silicon area.

Tree structure for mismatch noise-shaping multibit DAC

A sigma-delta analog to digital converter 1 is disclosed. The digital filter comprises digital integrators (8, 10) for reception of the negative feedback signal of the analog modulator. The digital integrators (8, 10) are connected to replicate processing of the feedback signal by the analog integrators (3, 5). Accordingly, the digital filter and the analog modulator may be reset simultaneously so that there is no time lag between conversion cycles. Thus, single shot operation is achieved.

Single shot sigma-delta analog to digital converter

Digital to Analog convertors (DAC's) are prone to mismatch noise, particularly in DAC structures using unequally weighted segments. A digital to analog converter, for use in a data conversion system, for converting a digital input to analog output and having features for reducing mismatch noise comprises a plurality of selectable segments, at least two of which have a first weighting factor and at least two of which have a second weighting factor. The segments when selected are connected to a reference signal, with the output for each segment, when selected, being proportional to the weighting factor of the segments. Selection means select segments based on the digital input. Summing means add the output from each selected segment to produce an analog output. The number of segments having the second weighting factor is equal to at least twice the ratio of the first and second weighting factors less one. Monitoring means monitor the number of times segments having the second weighting factor are selected in a given monitoring period and generate a correction signal when this number drops below a specified target selection value. Borrow means, responsive to the correction signal of the monitoring means, reduce the number of segments selected having the first weighting factor and increase the number of segments selected having the second weighting factor.

Mismatch noise shaper for DAC-SUBDAC structures

In a Sigma Delta converter, a succession of input signal samples are processed in an iterative manner to provide a succession of output signals and feedback signals, which are matched to the input signal samples over a specified frequency range. Two or more successive iterations are carried out in parallel so as to provide a sequence of independent outputs available in parallel. This provision of parallel outputs facilitates an overall increase in the speed of operation of the converter, which is otherwise limited by the maximum available rate of clocking of the converter's filters.

Parallel sigma delta modulator

Sigma delta modulators and pipelined (also called subranging) converters are used widely in Analog to Digital converters. In general pipelined converters are preferred where the highest speed of conversion is required and sigma delta converters are preferred for lower speed where a significant level of oversampling is possible. The present application describes a converter having the advantages of both types of converter. In particular, it discloses an analog to digital converter for converting an analog input signal ( 21 ) to a digital output signal ( 30 ), comprising a first converter having a filter means ( 25 ) for producing at least one filter output signal ( 31 ) by filtering the difference between the analog input signal and a feedback signal ( 32 ) generated from a first digital output, a quantizer ( 22 ) for producing the first digital output ( 28 ) by quantizing the weighted sum of a first filter output from the filter means and the analog input signal, a second converter for producing a second digital output by converting a second filter output ( 31 ) from the filter means ( 25 ), and a digital combiner ( 29 ) for combining the first output digital signal and the second output digital signal into the digital output signal.

Colin Lyden

Papers

Tree structure for mismatch noise-shaping multibit DAC

Single shot sigma-delta analog to digital converter

Mismatch noise shaper for DAC-SUBDAC structures

Parallel sigma delta modulator

A subranging sigma delta modulator