PROBLEM TO BE SOLVED: To provide a semiconductor device that overcomes the problem of the peeling of a through electrode and the problem of the peeling of a back wiring at the same time, by independently controlling the film thickness of the through electrode and the film thickness of the back electrode, in the semiconductor device having the through electrode and the back electrode formed integrally with the same, and to provide a method of manufacturing the same. SOLUTION: The semiconductor device includes a semiconductor substrate 10, a wiring layer 13 formed at the upper part of the semiconductor substrate and comprising at least one layer, a through electrode 30 reaching a wiring from the backside of the semiconductor substrate, a back wiring 40 provided on the backside of the semiconductor substrate and connected with the through electrode, and an external terminal 50 connected with the back wiring. The back wiring has the film thickness of a portion including at least connections with the external terminal formed thicker than the film thickness of the through electrode. COPYRIGHT: (C)2011,JPO&INPIT

Semiconductor device and method of manufacturing the same

A circuit for providing electrostatic discharge (ESD) protection is disclosed. The circuit comprises a pair of CMOS field effect pull up and pull down transistors with reduced resistance source and drain, having a well resistor formed external to them between supply and ground busses respectively. During an ESD event, the well resistors serve to both limit the current flow through the transistors, and reduce the voltage drop across them.

Well resistor for ESD protection of CMOS circuits

An ESD protection structure for I/O pads is formed with well resistors underlying the active areas of a transistor. The well resistors are coupled in series with the active areas and provide additional resistance which is effective in protecting the transistor from ESD events. Metal conductors over the active areas have a plurality of contacts to the active areas formed through an insulative layer to contact the active areas. Additional active areas adjacent to the active areas of the transistor are also coupled to the well resistors, and to a conductive layer which provides a conductor to the I/O pads. The active areas are silicided to reduce their resistance and increase the switching speed of the transistor. The n-well resistors are coupled in series to provide a large resistance with respect to that of the active areas to reduce the impact of ESD events.

Structure for esd protection in semiconductor chips

An FET with a lightly doped drain is connected between an input/output pad and ground and is protected from ESD at a pad by a structure that includes a resistor formed by the process step for the lightly doped drain. The resistor adjoins and interconnects a diffusion underlying the pad and the diffusion for the drain of the FET. A parasitic bipolar transistor is formed by the pad diffusion, the source diffusion for the FET, and the intervening substrate. When an ESD voltage appears at the pad, the FET conducts in circuit with the resistor and the voltage drop across the resistor helps to protect the FET and to turn on this parasitic bipolar transistor (in preference to a parasitic bipolar transistor otherwise formed by the FET) and thereby hold down the ESD voltage at the pad and at the drain of the FET. The FET and resistor can be formed as a number of parallel connected FETs and resistors located symmetrically on opposite sides of the pad diffusion. Protection for an input inverter circuit is also provided.

ESD protection device

A semiconductor integrated circuit having a diode element includes a diffusion layer which constitutes the anode and two diffusion layers which are provided on the left and right sides of the anode and which constitute the cathode, such that the anode and the cathode constitute the diode. A well contact is provided to surround both the diffusion layers of the anode and cathode. Distance tS between a longer side of the well contact and the diffusion layers of the cathode is shorter, while distance tL between a shorter side of the well contact and the diffusion layers of the anode and cathode is longer (tL>tS). Accordingly, the resistance value between the diffusion layer of the anode and the shorter side of the well contact is larger, so that the current from the diffusion layer of the anode is unlikely to flow toward the shorter side of the well contact. Thus, convergence of the current at the contact holes of the diffusion layer of the anode is reduced, so that the reliability of the diode element improves.

Semiconductor integrated circuit and system lsi including the same

A protection structure for integrated circuits with an n-channel MOS field-effect transistor has a more stable bipolar state, with the change to the bipolar state occurring fast. Below the drain region and the drain contact region an n-type resistor region doped more lightly than the drain region and the drain contact region is formed to provide the electrically conductive connection between the drain region and the drain contact region. When a positive voltage pulse is applied to the drain contact region, the n-channel MOS transistor will go into a bipolar operating state upon reaching the drain-source or drain-substrate breakdown voltage. The conductor paths are typically connected to ground. The n-well forms a series resistor between the drain region and the drain contact region of the respective transistor. It also forms a pn junction between the drain region and the channel, the collector pn junction, which extends deep into the substrate. Because of the series resistance of this n-well, during the change to the bipolar state, contractions of the current occurring at the pn junction are prevented. In the bipolar state, the transistor can absorb more power than with conventional arrangements. By connecting two or more transistors in parallel, the current is distributed even further, so that the power can be absorbed by both transistors, since the dissipation is distributed over an even larger area.

Cornelius Obermeier

Papers

IC protection structure having n-channel MOSFET with n-type resistor region