This ebook is the first authorized digital version of Kernighan and Ritchie's 1988 classic, The C Programming Language (2nd Ed.). One of the best-selling programming books published in the last fifty years, "K&R" has been called everything from the "bible" to "a landmark in computer science" and it has influenced generations of programmers. Available now for all leading ebook platforms, this concise and beautifully written text is a "must-have" reference for every serious programmers digital library.

As modestly described by the authors in the Preface to the First Edition, this "is not an introductory programming manual; it assumes some familiarity with basic programming concepts like variables, assignment statements, loops, and functions. Nonetheless, a novice programmer should be able to read along and pick up the language, although access to a more knowledgeable colleague will help."

The C programming language

This book attempts to achieve a difficult goal: to teach statistics to the novice so as to impart a liking and understanding of statistics. The book is geared toward a medical audience, since most examples are from the medical literature. The structure of the book consists of the following elements in each chapter: a small number of statistical rules of thumb, followed by a nontechnical explanation, a demonstration of how to work through the mechanics of doing the statistical test in question, a summary, and sample problems to be solved by the reader. (The answers, with explanations, are provided in an appendix.) Although a variety of univariate statistics are included, certain topics that are important in medical research are not. For example, there is little or no discussion of multiple regression, life-table techniques, or pooling of studies. These omissions, especially of multiple regression, are unfortunate. The Primer was derived from

Primer of Biostatistics

技術解説 IEEE Computer

Good news first: the international journal Computer Standards and Interfaces has a new editor-inchief, Dr. Bhavani Thuraisingham, professor of Computer Science at the University of Texas at Dallas. She is also a director of the bCyber Security Research Center Erik Jonsson School of Engineering and Computer ScienceQ. Dr. Thuraisingham was a member of the CS&I Editorial Board for long years and helped much to improve the journal’s reputation. She knows well the idea behind this unique journal, and she has the capacity and resources to lead and develop it. This is more than I expected when I decided to resign as editor-in-chief. The journal will be in good hands. At this occasion it should be allowed to have a look back. It was 1975 when I visited in the United States the National Bureau of Standards (NBS), later renamed in National Institute of Standards and Technology (NIST). With some interest could I see there lots of flyers and posters stating bGo metricQ. It was not that I didn’t know the bUS inchesQ. But I knew the bUnits ActQ of 1960 which was issued by the 11th General Conference of Weights and Measurement (CGPM) to introduce worldwide a unique International System of Units (SI) on a metrical basis. It was developed to put an end to more than a hundred years of disarray, with a great number of units and unit systems — and the metre was defined to be the unit of length representing 100 cm or 1000 mm. . . I was at that time a young scientist at the German national institute of metrology (PTB, Physikalisch-Technische Bundesanstalt) involved in the development of a calibration system for magnetic storage media like tapes, cassettes, flexible disks, disk packs etc. We did this in cooperation with the magnetic media lab of the

Next generation

The main problems associated with debugging concurrent programs are increased complexity, the "probe effect," nonrepeatability, and the lack of a synchronized global clock. The probe effect refers to the fact that any attempt to observe the behavior of a distributed system may change the behavior of that system. For some parallel programs, different executions with the same data will result in different results even without any attempt to observe the behavior. Even when the behavior can be observed, in many systems the lack of a synchronized global clock makes the results of the observation difficult to interpret. This paper discusses these and other problems related to debugging concurrent programs and presents a survey of current techniques used in debugging concurrent programs. Systems using three general techniques are described: traditional or breakpoint style debuggers, event monitoring systems, and static analysis systems. In addition, techniques for limiting, organizing, and displaying a large amount of data produced by the debugging systems are discussed.

Debugging concurrent programs

Advances in manufacturing technologies and in machine tools allow for unprecedented quality and efficiency in production lines, but also ask for new and increasing requirements on the motion planning and control systems. The increase of CPU processing power has permitted, in traditional CNC systems, the introduction of NURBS interpolation capabilities, thus determining a further increase in machining quality and efficiency. This has posed new and still unsolved issues, such as the need to satisfy multiple opposite constraints like limiting chord error, acceleration and jerk and offering real-time guarantees. In addition, the ability of privileging the production throughput by relaxing one or more of the previous constraints in a simple way, has emerged as another requirement of modern manufacturing plants. Nevertheless, none of the existing NURBS interpolators have these characteristics. In this work, we propose a NURBS interpolator that is able to satisfy all the manufacturing technology requirements and is able to respect, thanks to its bounded computational complexity, the position control real-time constraints. Such an interpolator is easily reconfigurable, i.e., it can relax some of the constraints while maintaining performances better than previously proposed solutions, and can be adapted in order to include constraints that were not originally considered. Performances of the proposed algorithm have been evaluated both by simulations and by real milling experiments.

A real-time configurable NURBS interpolator with bounded acceleration, jerk and chord error

We describe a simulator which emulates the activity of a shared memory, common bus multiprocessor system with private caches. Both kernel and user program activities are considered, thus allowing an accurate analysis and evaluation of coherence protocol performance. The simulator can generate synthetic traces, based on a wide set of input parameters which specify processor, kernel and workload features. Other parameters allow us to detail the multiprocessor architecture for which the analysis has to be carried out. An actual-trace-driven simulation is possible, too, in order to evaluate the performance of a specific multiprocessor with respect to a given workload, if traces concerning this workload are available. In a separate section, we describe how actual traces can also be used to extract a set of input parameters for synthetic trace generation. Finally, we show how the simulator may be successfully employed to carry out a detailed performance analysis of a specific coherence protocol. >

A trace-driven simulator for performance evaluation of cache-based multiprocessor systems

NUCA caches are large L2 on-chip cache memories characterized by multi-bank partitioning and designed to hide wire delay effects. They exhibit high hit rates while keeping access latency low. Proposed designs for such caches are Static NUCA, in which data are statically allocated to the cache banks, and Dynamic NUCA, in which data may reside in different banks, and a migration mechanism is introduced to better tolerate wire delay effects. The two architectures permit to achieve different performances by acting on architectural parameters and data management policies, at the cost of different balances between static and dynamic power consumption and energy dissipation. In this work, we propose preliminary results of the characterization of such balances, by presenting an evaluation of performance and energy consumption of conventional UCAs, and Static and Dynamic NUCA caches. All the considered caches architectures are equal sized and they are supposed to be used in an aggressive high frequency system running some applications from the SPEC CPU2000 and the NAS Parallel Benchmarks suites. The experimental results obtained indicate that, although the migration of data contributes to increase the dynamic energy consumption in Dynamic NUCA caches, the higher IPC achieved permits to save static energy, which dominates the power/energy balance in all the considered architectures. As a consequence, such results would designate NUCA caches as the most performing and energy saving architectures. Besides, according to the obtained results, future power improvements for NUCA caches should concentrate on static energy, while, for the dynamic energy, the on-chip network is the most critical element. Migration of data is acceptable, since it has a positive impact on performance, and the increased dynamic energy is overwhelmed by the static energy savings resulting from the shorter execution time. In order to give a general validity to such statements, we need to explore more design space points for each architecture (by varying the running clock rate and other design parameters) and to evaluate them considering a larger set of benchmarks.

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Analysis of static and dynamic energy consumption in NUCA caches: initial results

In high-performance general-purpose workstations and servers, the workload can be typically constituted of both sequential and parallel applications. Shared-bus shared-memory multiprocessor can be used to speed-up the execution of such workload. In this environment, the scheduler takes care of the load balancing by allocating a ready process on the first available processor, thus producing process migration. Process migration and the persistence of private data into different caches produce an undesired sharing, named passive sharing. The copies due to passive sharing produce useless coherence traffic on the bus and coping with such a problem may represent a challenging design problem for these machines. Many protocols use smart solutions to limit the overhead to maintain coherence among shared copies. None of these studies treats passive-sharing directly, although some indirect effect is present while dealing with the other kinds of sharing. Affinity scheduling can alleviate this problem, but this technique does not adapt to all load conditions, especially when the effects of migration are massive. We present a simple coherence protocol that eliminates passive sharing using information from the compiler that is normally available in operating system kernels. We evaluate the performance of this protocol and compare it against other solutions proposed in the literature by means of enhanced trace-driven simulation. We evaluate the complexity in terms of the number of protocol states, additional bus lines, and required software support. Our protocol further limits the coherence-maintaining overhead by using information about access patterns to shared data exhibited in parallel applications.

PSCR: a coherence protocol for eliminating passive sharing in shared-bus shared-memory multiprocessors

A major concern with high-performance general-purpose workstations is to speed up the execution of commands, uniprocess applications, and multiprocess applications with coarse- to medium-grain parallelism. The authors have developed a methodology and a set of tools to generate traces for the performance evaluation of shared-bus, shared-memory multiprocessor systems. Trace Factory produces traces representing significant real workloads consisting of a flexible set of commands and uniprocess and multiprocess user applications. The authors evaluate its accuracy and show how it can be used to evaluate and compare the performance of five coherence protocols.

Cosimo Antonio Prete

Papers

A real-time configurable NURBS interpolator with bounded acceleration, jerk and chord error

A trace-driven simulator for performance evaluation of cache-based multiprocessor systems

Analysis of static and dynamic energy consumption in NUCA caches: initial results

PSCR: a coherence protocol for eliminating passive sharing in shared-bus shared-memory multiprocessors

Trace Factory: generating workloads for trace-driven simulation of shared-bus multiprocessors