Recent advances in flexible and stretchable electronics (FSE), a technology diverging from the conventional rigid silicon technology, have stimulated fundamental scientific and technological research efforts. FSE aims at enabling disruptive applications such as flexible displays, wearable sensors, printed RFID tags on packaging, electronics on skin/organs, and Internet-of-things as well as possibly reducing the cost of electronic device fabrication. Thus, the key materials components of electronics, the semiconductor, the dielectric, and the conductor as well as the passive (substrate, planarization, passivation, and encapsulation layers) must exhibit electrical performance and mechanical properties compatible with FSE components and products. In this review, we summarize and analyze recent advances in materials concepts as well as in thin-film fabrication techniques for high-k (or high-capacitance) gate dielectrics when integrated with FSE-compatible semiconductors such as organics, metal oxides, quantum...

High- k Gate Dielectrics for Emerging Flexible and Stretchable Electronics

This invention discloses an improved semiconductor power device includes a plurality of power transistor cells wherein each cell further includes a planar gate padded by a gate oxide layer disposed on top of a drift layer constituting an upper layer of a semiconductor substrate wherein the planar gate further constituting a split gate including a gap opened in a gate layer whereby the a total surface area of the gate is reduced. The transistor cell further includes a JFET (junction field effect transistor) diffusion region disposed in the drift layer below the gap of the gate layer wherein the JFET diffusion region having a higher dopant concentration than the drift region for reducing a channel resistance of the semiconductor power device. The transistor cell further includes a shallow surface doped regions disposed near a top surface of the drift layer under the gate adjacent to the JFET diffusion region wherein the shallow surface doped region having a dopant concentration lower than the JFET diffusion region and higher than the drift layer.

Planar split-gate high-performance MOSFET structure and manufacturing method

Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.

Electronic circuits including a MOSFET and a dual-gate JFET

A mask is formed selectively on a crystalline silicon film containing a catalyst element, and an amorphous silicon film is formed so as to cover the mask. Phosphorus is implanted into the amorphous silicon film and the portion of the crystalline silicon film which is not covered with the mask. The silicon films are then heated by rapid thermal annealing (RTA). By virtue of the existence of the amorphous silicon film, the temperature of the crystalline silicon film is increased uniformly, whereby the portion of the crystalline silicon film covered with the mask is also heated sufficiently and the catalyst element existing in this region moves to the phosphorus-implanted, amorphous portion having high gettering ability. As a result, the concentration of the catalyst element is reduced in the portion of the silicon film covered with the mask. A semiconductor device is manufactured by using this portion.

Method of Manufacturing Semiconductor Device

A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

Semiconductor storage device

The present invention provides a JFET which receives an additional implant during fabrication, which extends its drain region towards its source region, and/or its source region towards its drain region. The implant reduces the magnitude of the e-field that would otherwise arise at the drain/channel (and/or source/channel) junction for a given drain and/or source voltage, thereby reducing the severity of the gate current and breakdown problems associated with the e-field. The JFET's gate layer is preferably sized to have a width which provides respective gaps between the gate layer's lateral boundaries and the drain and/or source regions for each implant, with each implant implanted in a respective gap.

JFET with drain and/or source modification implant

High dielectric constant, low loss dielectric thin film materials produced by reactive RF sputtering have been investigated for use as capacitor dielectrics in integrated circuits, using oxides of niobium, tantalum, titanium, hafnium, and zirconium and mixtures of these with aluminum oxide. High breakdown fields and low leakage currents are found for the best materials and a reduction in capacitor area of a factor of >3 compared with Si3N4 capacitors of the same value, using a simple production process compatible with semiconductor device manufacturing.

Thin film high dielectric constant metal oxides prepared by reactive sputtering

A layered capacitor structure comprises two or more semiconductor/dielectric plates formed above an insulating surface which provides mechanical support, with the plates arranged in a vertical stack on the insulating surface. An insulating layer is on each plate, patterned and etched to provide an opening which allows the top of one plate to be in physical and electrical contact with the bottom of the subsequent plate. Contact openings are provided through the insulating layers, each of which provides access to a respective semiconductor layer and is insulated from any other semiconductor/dielectric plate. Electrical contacts through the contact openings provide electrical connections to respective semiconductor layers. The present structure can include as many stacked layers as needed to provide a desired total capacitance or range of capacitances.

Layered capacitor architecture and fabrication method

High resistance, low temperature coefficient of resistance (TCR) thin-film resistors have been produced by rf sputtering from compound targets using the Cr–Si–B–SiO2/Al2O3 material system. After postdeposition annealing at 450–550 °C sheet resistances of 20 kΩ/sq and TCR<200 ppm/°C were obtained for films of 40 nm thickness. The effect of changes to the proportions of each component in the mixture was investigated and it was found possible to control resistance and TCR. X-ray photoelectron spectroscopic analysis showed a good correlation between the target and film compositions. X-ray diffraction investigation did not show any crystalline structure in the film either before or after thermal treatment.

High sheet resistance, low temperature coefficient of resistance resistor films for integrated circuits

A thin film composition is made from silicon, an insulator such as alumina or silicon dioxide, and at least one additional material such as chromium, nickel, boron and/or carbon. These materials are combined to provide a thin film having a p of at least 0.02 Ω-cm (typically 0.02-1.0 Ω-cm), and a TCR of less than ±1000 ppm/°C (typically less than ±300 ppm/°C). A sheet resistance of at least 20 kΩ/O may also be obtained. The resulting thin film is preferably at least 200 A (20nm) thick, to reduce surface scattering conduction currents.

Craig Wilson

Papers

JFET with drain and/or source modification implant

Thin film high dielectric constant metal oxides prepared by reactive sputtering

Layered capacitor architecture and fabrication method

High sheet resistance, low temperature coefficient of resistance resistor films for integrated circuits

High resistivity thin film composition and fabrication method