C
Cristina Silvano
Researcher at Polytechnic University of Milan
Publications - 198
Citations - 3896
Cristina Silvano is an academic researcher from Polytechnic University of Milan. The author has contributed to research in topics: Design space exploration & Compiler. The author has an hindex of 34, co-authored 194 publications receiving 3635 citations. Previous affiliations of Cristina Silvano include University of Milan & University of Lugano.
Papers
More filters
Proceedings ArticleDOI
Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems
TL;DR: In this article, the authors propose an encoding scheme which is suitable for reducing the switching activity on the lines of an address bus, which relies on the observation that, in a remarkable number of cases, patterns traveling onto address buses are consecutive.
Proceedings ArticleDOI
Address bus encoding techniques for system-level power optimization
TL;DR: This paper presents innovative encoding techniques suitable for minimizing the switching activity of system-level address buses, and targets the reduction of the average number of bus line transitions per clock cycle.
Journal ArticleDOI
ReSPIR: A Response Surface-Based Pareto Iterative Refinement for Application-Specific Design Space Exploration
TL;DR: An efficient DSE methodology for application-specific MPSoC is proposed that is efficient in the sense that it is capable of finding a set of good candidate architecture configurations by minimizing the number of simulations to be executed.
Journal ArticleDOI
Secure Memory Accesses on Networks-on-Chip
TL;DR: This paper presents a secure NoC architecture composed of a set of data protection units (DPUs) implemented within the network interfaces, and focuses on the dynamic updating of the DPUs to support their utilization in dynamic environments, and on the utilization of authentication techniques to increase the level of security.
Journal Article
Multi-objective design space exploration of embedded systems
TL;DR: A Design Space Exploration (DSE) framework to simulate the target system and to dynamically profile the target applications and to reduce the overall exploration time by computing an approximated Pareto set of configurations with respect to the selected figures of merit.