: This chapter provides an overview of complex integrated circuit technology, focusing particularly upon application specific integrated circuits. This report is intended to assist FAA certification engineers in making safety assessments of new technologies. It examines complex integrated circuit technology, focusing on three fields: design, test, and certification. It provides the reader with the background and a basic understanding of the fundamentals of these fields. Also included is material on the development environment, including languages and tools. Application specific integrated circuits are widely used in Boeing 777 fly-by-wire aircraft. Safety issues abound for these integrated circuits when they are used in safety-critical applications. Since control laws are now executed in silicon and transmitted from one integrated circuit to another, reliability issues for these integrated circuits take on a new importance. This report identifies certification risks relating to the use of complex integrated circuits in fly-by-wire applications.

Digital Systems Validation Handbook, Volume 3. Design, Test, and Certification Issues for Complex Integrated Circuits - Chapter 2.

Building and running Spatio-Temporal Exploration and Analysis (STEA) queries for today's flavors of databases and Geographic Information Systems (GISs) is a difficult task. The iterative navigation from general views (coarse granularity) to very detailed views (fine granularity) according to multiple themes implies running large queries against large volumes of data in reasonable time. In some cases, users lose their “train-of-thought” due the long query run times. In others, users lose their “ train-of-thought” due to the complexity of the query language. In order to interface effectively with human cognitive systems, systems aimed at supporting STEA must comply with principles of human spatial cognition. Among these principles, hierarchies, topology, the coupling of geographic space and time and short query run times are essential. 
The goal of this thesis is propose a new data structure, the Spatio-Temporal Topological Operator Dimension (STTOD), which implements a hierarchy of spatio-temporal topological operators in a multidimensional database (MDDB) to support STEA. This hierarchy covers the three possible domains of spatio-temporal topological constraints e.g. spatial, temporal and spatio-temporal. Operators at the highest level carry general meanings while operators from the lowest levels have very specific meanings. This hierarchy is structured according to multiple levels of granularity based on cognitive models, generalized relationships and formal models of topological relationships. The topological relationships are described either through groups of operators or through the ISO/TC 211 9-intersection method (9IM) developed by Egenhofer and Herring (1994) and the DE + 9IM developed by Clementini and Di Felice (1994). This research followed an experimental type of research to implement and to test the validity of the STTOD in the context of Automatic Position Reporting System (APRS), the amateur radio system for position report transmission. 
We demonstrated that the implementation of the STTOD allows adequate STEA by permitting spatio-temporal topological analysis within the multidimensional approach. We also demonstrated that such an implementation offers query run times which permit to maintain a “train-of-thought” during as they are compatible with Newell's (1990) cognitive band. This proposed solution represents a new approach for rapid and intuitive STEA while being generic, software-independent and implementable in today's commercial MDDBs.

The spatio-temporal topological operator dimension, a hyperstructure for multidimensional spatio-temporal exploration and analysis

We are now witnessing a proliferation of integrated circuit solutions to several signal processing and related problems. This has motivated the evolution of High Level Synthesis (HLS) where the objective is to obtain an efficient register-transfer level (RTL) realization of a target system from its behavioural specification. An important aspect of HLS is the Data Path Synthesis (DPS) problem, which concerns the construction of optimal data paths of the target system. In this work we examine the complexity of several DPS problems and propose solutions to them. The overall objectives of this work are characterization of the complexity of the synthesis problem and proposing solutions to major tasks involved in DPS. We have, in general, considered the hardness of the problem in question and also the hardness of its approximation schemes. We have found that several interconnect optimization problems, like port assignment of multi-port memories, register-interconnect optimization and allocation and binding, are NP-hard and their relative approximations are also NP-hard. A few scheduling problems, on the other hand, can be solved optimally in polynomial time. List scheduling sometimes guarantees a 2-approximate solution under some conditions. A number of scheduling problems and their constant approximations are also NP-hard. To the best of our knowledge the complexity of relative approximation of many scheduling problems, of interest in DPS, is open. We have proposed solutions to some individual interconnection oriented sub-problems of data path synthesis and solution to the entire DPS problem. We have made use of heuristic techniques, controlled search and genetic algorithms as problem solving tools. The individual sub-problems are register-interconnect optimization (RIO), memoryinterconnect optimization (MIO) and port assignment (PA) of dual and triple port memories. For RIO and MIO we use heuristic techniques, whereas the PA problems are solved using genetic algorithms. For the entire DPS problem we have adopted an approach based on a design space exploration. Instead of finding a single design from a given behavioural specification, we seek to find a set of competitive designs which satisfy the specification. We have proposed a two phase solution to the entire synthesis problem. In the first phase we find a set of competitive schedules through design space exploration, based on controlled search and heuristic methods. We have also developed a genetic list scheduling technique to work with our DSE technique. In the second phase we find the data paths for each of these schedules through allocation and binding using a genetic algorithm approach.

Complexity Analysis and Algorithms for Data Path Synthesis

The design space for VLSI circuits and systems is multidimensional since area, delay, power, design time, throughput, etc. are factors affecting the designer's choice of an optimum implementation. Presently, most designers lack the resources or tools to consider simultaneously more than two of these dimensions (e.g. area and delay). In this paper, a new approach is presented which facilitates the simultaneous consideration of multiple dimensions to increase the likelihood of finding a globally optimum solution. Furthermore, the new approach enables the designer to explore a larger number of candidate solutions and to prune the design space before pursuing more detailed implementations. A formal definition of the new approach is given along with several examples that depict its strength in assisting VLSI designers. >

Early exploration of the multi-dimensional VLSI design space

A new DFT implementation incorporating distributed arithmetic with the DFT is reported. This method proves to be faster and to require less area than the direct implementation of the FFT. >

D.B. Koch

Papers

Early exploration of the multi-dimensional VLSI design space

A fast implementation of the distributed arithmetic discrete Fourier transform